A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell

Approximate Memory for Low-Power Video Applications

“…Reference [9] also utilized adaptability, where no ECC, ECC74, or ECC1511 could be selected at runtime to trade off lower power for higher quality depending on the application. For this work, adaptability was also considered; however, when including the additional hardware required for adaptability, the resulting system required more power than simply hardening all 16 bits using the differential wordline bitline method [13] discussed in the above previous work section. Since hardening all bits results in 0 errors (i.e., PSNR = ∞) and required less power than adaptability, adaptability between ECC schemes was not considered further.…”

“…However, for those designs, memory cells in the same word operate at different voltages, such that voltage conversion induces additional area overhead. To minimize this area overhead, Keshavarapu et al [13] studied the read and write noise margins and concluded that read failures would be reduced if a cell's bitline supply voltage is higher than its wordline voltage. Herein, we adapt this ''hardening'' technique for selective MSBs.…”

“…In our proposed memory architecture, a low-cost hardening technique is adapted based on [13], where the wordline supply voltage is lower than the bitline's to increase the memory cell's read noise margin, thereby reducing its read failure rate. Since read failures dominate total failures for 6T bitcells at low voltages, this read-assist technique can be used to avoid memory failures, which thereby achieves a form of hardening.…”