A new buried-gate VMOSFET with suppressed overlap capacitance and improved electrical characteristics

Abstract

This study presents a new buried-gate vertical MOSFET (BGVMOS) with suppressed overlap capacitance and improved electrical characteristics due to its modified gate structure. According to the TCAD simulations, our proposed BGVMOS structure can gain reduced parasitic capacitances (27.11% C gd and 37.53% C gs at V Ds = 1.0 V), improved drain saturation current, and free kink effect, in comparison to a conventional VMOS (CVMOS) structure. Most importantly, the reduced surface scattering in the BGVMOS helps improve the drain current and the transconductance mainly owing to the 1/4 circle gate scheme which is difficult task for a CVMOS transistor. IntroductionIt is more and more difficult to use a planar bulkSi-based single-gate (SG) MOSFET for VLSI applications because of the short-channel effects (SCEs). According to the international technology roadmap for semiconductors (ITRS), the SCEs are difficult to be controlled by using only a SG scheme [1], [2]. One of the solutions is to use a double-gate (DG) field-effect transistor (FET) due mainly to its coupling effects between the top gate and bottom gate. The DG device can not only suppress the SCEs but also improve the transconductance [3], [4]. Although both the processes of the conventional SG and DG devices are compatible to the CMOS technology, the processes of photolithography and the etching for the scaled gate length (L G ) formation are difficult to be realized [4]. Thus, the vertical MOS (VMOS) with DG structure has been considered to be one of the novel device architectures for solving the issues mentioned above. Unfortunately, a large Miller capacitance presented in a conventional VMOS (CVMOS) structure seriously decreases the high 3-dB frequency and affects bandwidth properties. Hence, a large gate-to-source capacitance (C gs ) and a large gate-to-drain capacitance (C gd ) in a CVMOS are shown and compared with a planar bulkSi MOSFET, leading a decrease in the small-signal performance [5], [6].