A new CDM test method and protective circuits against the excessive mobile charge

Abstract

In the charged device model (CDM) test, the relationship between the failure voltage, the capacitance of LSIs and the failure charge was made clear by a new CDM tester. The mobile charge measurement apparatus was fabricated in the tester, and the capacity and the charge could be measured simultaneously in the CDM test. The CDM sensitivity of the logic MOS LSIs was represented as an inherent quantity of charge for each LSI. Furthermore, using the experimental results, a basic protection circuit to withstand the high quantity of charge in the CDM test was described. The practical use of the data gives us methods to prevent electrostatic discharge (ESD) trouble for quarter-micron LSIs.

Problems of the human body model and electrostatic discharge part 1: discharge from LSIs held by a charged person

“…Although the HBM failure voltage for the LSI was 2.3-2.5 kV, the failure voltage for the hand-held LSI was 1.0-1.7 kV, nearly equal to 0.9-1.2 kV of the CDM test. The detailed CDM test method has been mentioned elsewhere [8]. This result agreed well with the abovementioned preliminary experiments.…”

“…This means that all the elements constituting the inner conductor in the LSI are at a uniform electric potential in supplying the high voltage to a pin of the LSI. The phenomenon has previously been verified by experiments [7]. However, the peak current and the pulse width depended on the device size, for example the area of the inner conductor in the LSI package.…”

“…Although the robustness of the conventional ESD has been specified by merely the voltage V , the capacitance C is an important factor in order to prevent the many ESD accidents for current VLSIs. The Q, C and V of the charged objects including LSIs can be determined by the application of the above-mentioned method [6,7]. We expect that the experimental results in this paper will contribute greatly to progress with quarter-micron VLSIs.…”

Problems of the human body model and electrostatic discharge part 2: the HBM test for non-wired pins of LSIs

“…C LG was a capacitance between an internal conductor of the LSI and the ground plane. The tested LSI in this paper showed the failure charge Q D = 18 nC in the CDM test with variable C LG (7-10 pF) [10]. First, the difference between 62 nC (for C 2 = 19.8 pF) and 18 nC may be dependent on the transient responses of the protective circuit fabricated in the LSI chip.…”

The use of the coulomb meter to measure the excess mobile charge and capacitance of LSI circuits in the charged device model

“…Thus, it was guessed that the failure factor of MOS elements also could not be represented by only the voltage. Recently, we reported the MM failure factor of recent PN junction devices [6] and the CDM failure factor of logic MOS LSIs [6,7]. This is a summary of the paper [6].…”