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In the charged device model (CDM) test, the relationship between the failure voltage, the capacitance of LSIs and the failure charge was made clear by a new CDM tester. The mobile charge measurement apparatus was fabricated in the tester, and the capacity and the charge could be measured simultaneously in the CDM test. The CDM sensitivity of the logic MOS LSIs was represented as an inherent quantity of charge for each LSI. Furthermore, using the experimental results, a basic protection circuit to withstand the high quantity of charge in the CDM test was described. The practical use of the data gives us methods to prevent electrostatic discharge (ESD) trouble for quarter-micron LSIs.

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