A new characterization of sub-μm parallel multilevel interconnects and experimental verification

Abstract

This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film (Si3 N4) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design.

An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits

“…In [12], it was identified that the 3-D crossings (crossover) is a critical component in the total wiring capacitance, and a linear model with different components was then proposed with linear dependence on area, periphery length, and spacing. The work of Aoyama et al [13] characterized coupling and ground capacitance using test patterns and numerical solutions, and it provided an optimization study by wire pitch to dielectric thickness ratio. The work of Chao et al [14] presented a novel extraction methodology and test pattern, with verifications on SOG and CMP processes.…”

Accurate statistical process variation analysis for 0.25-μm CMOS with advanced TCAD methodology

“…Therefore the circuit and chip designer needs to estimate the statistical variation of process and device characteristics through the terms of worst case and/or statistical (circuit) design parameters before actual mass-production phase. Especially in high-speed MPU and ASIC design, predictive accurate variation analysis is more important since clock-delay [1] and skew specifications become increasingly tighter in high clock cycle VLSI's. In this respect the precise estimation of process variation effects and practical worst case circuit design parameters are key design issues in 0.25-m CMOS LSI's before actual mass-production phase.…”