Abstract-Effects

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This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film (Si3 N4) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design.

A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM ( Response Surface Method ) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process / device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development.

An industrial statistical worst case modeling for 0.2pm CMOS is presented. It is based on new TCADprototyping with &dent correlation analysis for CMOS performance goals under process variability . Since the manufacturing process undergoes ongoing iniprovenent, well-calibrated TCAD is primary tool to construct realistic performance corner models. Robust TCAD calibration method is one of the key to achieve the accurate prediction. Statistically least conservative "Worst case" conditions are newly identified, which states 99.7%of device performance is contained b e -' the FF (Fast Fast) and SS (Slow Slow) worst corners. This reduces design guardband by lo%, compared with conventional Worst case approaches.