A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

Maryan, Mohammad Moradinezhad; Amini-Valashani, Majid; Azhari, Seyed Javad

doi:10.1007/s00034-020-01639-9

Cited by 18 publications

(10 citation statements)

References 35 publications

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“…On the other hand, to examine the results more accurately, it is better to involve the other parameters in the concept of noise margin such as PDP and area consumption which are defined as the Width (nm) × number of transistors in this case. A higher value of the defined figure of merit (FoM) shows a better design [45]. In this regard, it can be seen that the proposed circuit with less PDP has the highest FoM compared to other cells.…”

Section: Simulation Setup Results and Comprehensive Analysismentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

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A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

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Section: Simulation Setup Results and Comprehensive Analysismentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

show abstract

“…The conceptual block diagram of the proposed input controlled leakage restrainer transistor (ICLRT) 25 approach for leakage and short-circuit power reduction is depicted in Figure 3. The main idea of this technique is that in any condition of input signals there are at least two cutoff transistors between the supply voltage and the ground in standby mode.…”

Section: Proposed Circuit-level Techniquementioning

confidence: 99%

“…In active mode, leakage current (mainly produced by gate-oxide tunneling current) is reduced by gate-source voltage reduction, stack effect, and transistor width reduction. 25 To implement this method, like Figure 4A,B,E, an NMOS ICLRT is placed below the PDN and a PMOS ICLRT is located on top of the PUN for static CMOS gates that is depicted in Figure 3A.…”

Section: Proposed Circuit-level Techniquementioning

confidence: 99%

“…The block diagram of the proposed ICLRT technique, 25 voltage of transistor M N , V N > 0 (V P < V DD ), the gate-to-source voltage of M N (M P ) becomes negative (positive) thus, the subthreshold current is greatly reduced. In this case, due to V N > 0 (V P < V DD ), the body-to-source voltage of M N decreases (M P increases) resulting in increasing the V TH that reduces the subthreshold leakage current.…”

Section: Main Sources Of Leakage and Short-circuit Currents Using Iclrt Techniquementioning

confidence: 99%

“…Also, due to the stack effect of applied ICLRTs, the gate-oxide leakage current is also diminished. 25 In switching mode, both M N and M P transistors are ON (saturation region) and short-circuit current flows in a path from V DD rail to the ground rail, therefore based on Equation ( 6), the smaller V GS along with higher V TH of M N and M P , resulting in lower short-circuit current and power.…”

Section: Main Sources Of Leakage and Short-circuit Currents Using Iclrt Techniquementioning

confidence: 99%

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An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

Maryan

Amini-Valashani

Azhari

2021

Circuit Theory & Apps

Self Cite

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The sharp increase in the leakage part of the total power of the very large scale integration (VLSI) circuits is a significant concern in the deep submicron CMOS process. The NOT gates, Gate Diffusion Input (GDI) cells, restorer NMOS-PMOS transistors for full-swing operation, and any path from the power voltage to the ground are the main sources of leakage power dissipation as well as short-circuit in the VLSI CMOS circuits/chips. The input controlled leakage restrainer transistor (ICLRT) is a new circuit-level method that is proposed in this paper. The ICLRTs can be deliberately added to any VLSI CMOS circuit to largely diminish the total power dissipation especially by the reduction of its leakage and short-circuit parts. The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1-bit hybrid full adders in the deep submicron process to fit the needs of the day. The efficiency of the proposed method is evaluated using SPICE simulations in 22-nm CMOS BSIM4 process. Evaluation outcomes with 1-V power supply verified that the power dissipation and power-delay product (PDP) of the hybrid full adders based on ICLRT technique relative to corresponding original designs are reduced 65.67-95.7% and 35.85-87.37%, respectively. Mismatch analysis and Monte Carlo simulations prove the robustness and stability of the presented circuits in the presence of the process, voltage, and temperature (PVT) variations.

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One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Darabi

Salehi

Abiri

2022

Circuit Theory & Apps

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This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms.

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A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

Cited by 18 publications

References 35 publications

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

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