A new CMOS comparator robust to process and temperature variations for SAR ADC converters

Fuente-Cortes, Gisela De La; Flores‐Verdad, Guillermo Espinosa; González-Díaz, Víctor R.; Díaz-Méndez, Alejandro

doi:10.1007/s10470-016-0916-9

Cited by 18 publications

(9 citation statements)

References 7 publications

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“…P @i , P @j and P overall are representing the power of Comp1, Comp2 and 11th-bit power, respectively, including both comparisons, where @i, @j, is the noise voltage for Comp1 and Comp2, respectively. Additionally, the step input response can be found on the complete circuit when spider-latch and amplifiers are active as in de La Fuente-Cortes et al (2017).…”

Section: Performance and Resultsmentioning

confidence: 99%

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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Section: Performance and Resultsmentioning

confidence: 99%

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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“…Table 7 gives details regarding the comparison on the basis of power consumption of this comparator with other pertinent associated studies. [32] 130 nm 1.0 V 130 nm 100 µW [33] 180 nm 1.1 V -180 nm 1300 µW [34] 180 nm --180 nm ∼ =750 µW [35] 65 nm 1.2 V -65 nm 2800 µW [36] 65 nm 1.2 V 65 nm 370 µW [37] 180 nm 0.7 V to 1.1 V 180 nm 420 µW GB-CMFD (Proposed-architecture) 90 nm 0.7 V 839 V/µs 90 nm 362 µW…”

Section: Discussionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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“…To reduce the power consumption, there are many diferent methods, as will be demonstrated in this paper. Various confgurations for the comparator [14][15][16][17][18][19][20][21][22][23][24] can be used to reduce power consumption, time delay, and noise efects. In addition, the modifed binary-weighted CDAC structure can save area and energy.…”

Section: Sar Adc Architecturementioning

confidence: 99%

“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”

Section: Sar Sample and Hold Circuitmentioning

confidence: 99%

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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A new CMOS comparator robust to process and temperature variations for SAR ADC converters

Cited by 18 publications

References 7 publications

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

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