A new compact analytical model of single electron transistor for hybrid SET–MOS circuits

Jain, Amit; Nameriakpam, Basanta Singh; Sarkar, Subir Kumar

doi:10.1016/j.sse.2014.11.019

Cited by 10 publications

(2 citation statements)

References 24 publications

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“…By cross-checking findings using the Monte Carlo simulator SIMON, the correctness of the model is verified. The model may be used in conjunction with the SPICE environment and is created on the Verilog-A language platform [40]. The "ortho-dox theory" of single electron tunneling serves as the foundation for the proposed compact analytical single electron transistor (SET) model.…”

Section: Set Modeling Reviewmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Shruti Suman

2024

jes

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Gordon Moore's "Moore's Law" suggests chip functionality demand doubles every 1.5-2 years, with global semiconductor technology roadmap recommending sub-nanometer ranges for IC production in nano-electronics. The single electron transistor (SET) is a promising nano-scale device that can be co-integrated with CMOS technology to improve performance. The paper explores the tunnelling effect between nanoparticles in single electron transistors (SET), revealing coulomb blockade transactions and resistance increases with reduced bias. It focuses on single electron transistors and pre-terminal devices, discussing IV characteristics, coulomb diamond plots, and metallic quantum dots. This research also explores the hybrid SET-FET based model, focusing on developing a room temperature SET in CMOS comparable technology with a Field Effect Transistor (FET). Prediction models and exploratory studies guide the integration of SET-FET technology. SIMON is a comprehensive simulator designed for single-electron devices and circuits. The output current is not impacted by capacitances up to 1 pF, and FET size in the micron range are appropriate for SET signal amplification up to 4 µA. This research explores the modelling of SET-FET technology in highlighting its ability to mitigate drawbacks in low drive current when combined with a FET. It also explores device variability mitigation in nanoscale array configurations, finding that SET-FET significantly reduces variability in larger arrays, despite the impact of capacitance and resistance.

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Section: Set Modeling Reviewmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Shruti Suman

2024

jes

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“…[1][2][3][4] Apart from a well-accepted simulator (SIMON), there are a few models of single electron transistor (SET) which have been used extensively by the researcher for simulating single electronics circuits. [5][6][7][8][9] Due to the lower gain of single electronics devices compared with its CMOS counterpart, they are mostly used in the circuits designed targeting digital applications. [10][11][12][13][14] So the switching speed or more specifically the delay analysis of these devices needs to be studied extensively for proper designing of practical integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

Error probability independent delay analysis of single electronics circuits

Jain

Ghosh²,

Dutta

et al. 2017

Circuit Theory & Apps

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This study based on Poisson process and orthodox theory of single electron tunneling for the first time proposes an error probability independent delay model for delay calculation of single electronics circuits, involving multiple tunneling events. The Poisson process assumes that the tunneling events are independent of each other, but in real single electronics circuits they are correlated through space and time, so this effect has been considered and included in the proposed model. The dependence of tunneling rates on the logic transition is thoroughly investigated. Finally, the model is applied to different logic gates, and the result is compared with the well known Monte Carlo approach to prove the accuracy of the proposed model.

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