A new design methodology for multiport SRAM cell

Abstract

In this paper, we propose a new design methodology for multiport SRAM cell. A traditional static 6T CMOS cell is adapted to the multiport SRAM cell by adding several wordline transistors, thereby allowing asynchronous reads and writes during an operands access stage using the read feature of the 5T cell and the write feature of the 6T cell. The stability of the SRAM cell is affected by the factors of p-transistor, n-transistor and passtransistor, not by the absolute dimensions of the three transistors. The optimal read access curve can be used to obtain the fastest access time in the secure range for the general multiport SRAM cell.