A new efficient memoryless residue to binary converter

Andraos, S.; Ahmad, Hamzeh J.

doi:10.1109/31.14470

Cited by 109 publications

(32 citation statements)

References 3 publications

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“…The algorithm uses four adders, two of which operate in parallel, to convert the moduli (2 n + 1, 2 n , 2 n − 1) residue number into their binary equivalent. Recently, Piestrak 11) suggested a simplification of the Andraos-Ahmad technique: the value of the −r 1 modulo 2 2n−1 of Andraos, et al 10) can be easily obtained by manipulating r 1 . Piestrak 11) proposed two methods.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

“…Piestrak 11) proposed two methods. The first method, referred to as the cost-effective (CE) version, uses two 2n-bit CSAs and one 2n CPA with an end-around-carry to calculate the A + B + C − r 1 of Andraos, et al 10) . The other method, which is referred to as the high-speed (HS) version, uses two 2n-bit CSAs and two parallel 2n-bit CPAs followed by a multiplexer.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

“…A number of residue-to-binary number converters have been proposed 10)∼12) for the moduli set (2 n − 1, 2 n , 2 n + 1). The algorithm of Andraos et al 10) uses multiplicative inverses to simplify the CRT and that of Piestrak 11) is an improved algorithm. Arithmetic modulo 2 2n − 1 is required, and the implementation units of carry save adders (CSAs) and multiplexers improve its speed.…”

Section: Introductionmentioning

confidence: 99%

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Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1)

Chen

Wei

2006

ipsjdc

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High-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-toweighted (RTOW) number conversions with the moduli set (2 n , 2 n − 1, 2 n + 1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW number conversions result in simpler hardware requirements for the converters. The primary advantages of our method are that our conversions use the modulo m signed-digit adder (MSDA) only and that the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation using circuit designs and a simulation, and the results show the importance of SD architectures for WTOR and RTOW number conversions. Compared to other converters, our methods are fast and the execution times are independent of the word length. We also propose a high-speed method for converting an SD number to a binary number representation.

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Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1)

Chen

Wei

2006

ipsjdc

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“…The reason is that these ranges are efficient for S 0 and the entire binary ranges can be accommodated by the proposed architectures with an additional combinational circuit or ROM for the overflow cases; this will introduce additional complexity. The implementation of the 8-bit, 16-bit, 32-bit and 64-bit converters of S 0 for the 2 8 2 1, 2 16 2 1, 2 32 2 1, and 2 64 2 1 ranges based on the special sets are shown in Table III.…”

Section: Vlsi Implementationmentioning

confidence: 99%

“…Here, we only show the implementation of the converters based on S 0 . For this implementation, the 2 8 2 1, 2 16 2 1, 2 32 2 1, and 2 64 2 1 ranges are chosen instead of the four entire binary ranges. The reason is that these ranges are efficient for S 0 and the entire binary ranges can be accommodated by the proposed architectures with an additional combinational circuit or ROM for the overflow cases; this will introduce additional complexity.…”

Section: Vlsi Implementationmentioning

confidence: 99%

A Parallel Residue‐to‐binary Converter for the Moduli Set {2m−1111,220m+,221m+,…,22km+}

Wang¹,

Swamy²,

Ahmad³

et al. 2000

VLSI Design

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In this paper, a high-speed parallel residue-to-binary converter is proposed for a recently introduced moduli set S k ¼ {2 m 2 1; 2 2 0 m þ 1; 2 2 1 m þ 1; . . .; 2 2 k m þ 1} for a general value of k. The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases of k ¼ 0 and k ¼ 1 are derived from the general architecture and compared with those existing in the literature. The converter for S 0 is twice as fast requiring only onehalf of the hardware, while that of S 1 is three times as fast, but requiring only 60% of the hardware, as compared to the corresponding ones existing in the literature. Furthermore, the proposed converters are implemented using 0.5-micron CMOS VLSI technology. Based on S 0 , the layouts for 8-bit, 16-bit, 32-bit and 64-bit converters are generated, and the corresponding simulation results obtained. INTRODUCTIONDuring the past decade, the residue number system (RNS) arithmetic has received considerable attention in arithmetic computation and signal processing applications, such as the fast Fourier transform, digital filtering and image processing. The main reasons for this attention are the inherent properties enjoyed by the RNS such as parallelism, modularity, fault tolerance and carry free operations [2 -4]. The crucial step for any successful RNS application is the residue-to-binary (R/B) conversion. In recent years, the conversion process has been studied very extensively [5 -20].In order to use the RNS to represent binary numbers, a moduli set has to be chosen. Recently, several new moduli sets have been proposed [5 -9]. One such set is S k ¼ {2 m 2 1; 2 2 0 m þ 1; 2 2 1 m þ 1; . . .; 2 2 k m þ 1}, for which the R/B converters for the cases of k ¼ 0 and k ¼ 1 have been also proposed [5]. According to Ref [5], this moduli set is expected to play an important role in the RNS, since the multiplications in the R/B conversion of this moduli set have been replaced by simple shift operations of signed-digit numbers. It has been shown in Ref.[5] that the R/B converter for S k is much faster and simpler compared to the existing converters. For 8-bit dynamic range, the FA-based R/B converter of Ref.[10] requires 837 transistors with 51 gate delays while the converter based on S k of Ref.[5] requires only 510 transistors with 38 gate delays. However, no R/B converter for S k has been designed so far for k $ 2: Since more than two or three moduli must be considered for large dynamic ranges [11], an introduction of the converter for a general k is essential.In this paper, we propose a high-speed parallel R/B converter for the general moduli set S k ; this converter also uses no multipliers. Instead of shifting the signed-digit numbers, we use simple cyclic shift and concatenation operations. For the purpose of comparison, the individual converters for the cases of k ¼ 0 and k ¼ 1 are derived from the general architecture. The new converter for S 0 is twice as fast as the one in Ref.[5] requiring only one-ha...

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RNS‐Based Arithmetic Circuits and Applications

Meher

Stouraitis²

2017

Arithmetic Circuits for DSP Applications

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A new efficient memoryless residue to binary converter

Cited by 109 publications

References 3 publications

Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1)

Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1)

A Parallel Residue‐to‐binary Converter for the Moduli Set {2m−1111,220m+,221m+,…,22km+}

RNS‐Based Arithmetic Circuits and Applications

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