A new empirical nonlinear model for sub-250 nm channel MOSFET

Siligaris, Alexandre; Dambrine, G.; Schreurs, Dominique; Danneville, F.

doi:10.1109/lmwc.2003.815687

Cited by 23 publications

(4 citation statements)

References 7 publications

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“…G m1 is the large-signal transconductance of M 1 , equal to the ratio of the fundamental harmonic of the drain current of M 1 to the fundamental harmonic of the gate-source voltage of M 1 . For transistor M 2 , a simplified largesignal equivalent circuit is used [34,35]. This equivalent circuit is obtained by considering the simplified transistor model with the large-signal transconductance (G m ), gate-to-source capacitance (C GS ), gate-to-drain capacitance (C GD ), source-to-bulk capacitance (C SB ), drain-to-bulk capacitance (C DB ), and output resistance (R DS ).…”

Section: Chlis D Pepe and D Zitomentioning

confidence: 99%

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Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Chlis

Pepe²,

Zito

2015

Circuit Theory & Apps

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SUMMARYThis paper reports the analyses of three techniques for phase noise reduction in the complementary metaloxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz.

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Section: Chlis D Pepe and D Zitomentioning

confidence: 99%

“…Furthermore, we can substitute V GS1 in (35) with its value given by (31). Using (31) and (33) into (34), solving with respect to V x and substituting for V x in (35), G m,eq1 can be written as…”

Section: Optimum Inductance For Minimum Phase Noisementioning

confidence: 99%

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Chlis

Pepe²,

Zito

2015

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…It should be pointed out that, to build a large‐signal FET model, the intrinsic elements should be extracted from multi‐bias S‐parameters measured over a grid of bias voltages . This bias grid should be dense to guarantee good interpolation properties and wide enough to cover most of the relevant bias conditions within the safe operating area (SOA), beyond which the FET may be damaged.…”

Section: The Active Role Of the Transconductancementioning

confidence: 99%

The large world of FET small-signal equivalent circuits (invited paper)

Crupi

Caddemi

Schreurs

et al. 2016

Int J RF and Microwave Comp Aid Eng

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The small-signal equivalent circuit modeling of microwave field-effect transistors (FETs) is an evergreen and ever flourishing research field that has to be up-to-date with technological developments. Hence, modeling techniques must be continuously adapted and extended to suit best evolving technologies. The extraction of a FET high-frequency small-signal equivalent circuit is a very active and broad research area of significant interest, owing to its use as a prerequisite for noise and large-signal modeling. The aim of this invited article is to provide in-depth knowledge, critical understanding, and new insights into how to extract a FET small-signal equivalent circuit from both theoretical and practical perspectives. To illustrate potential solutions to the key challenges faced by researchers, experimental results for different semiconductor technologies are reported and discussed. The study is focused on the hot research topic of the cold approach that has been, and still is, the most widely used technique for extracting FET small-signal models and on the active role of the transconductance for successful modeling. V C 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:749-762, 2016.

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“…The multilayered structure of the dielectric with numerous silicon-dioxide and silicon-nitride layers was simplified using Kraszewski formulation for effective permittivity [9]. The large-signal RF MOSFET model was developed for sub-250-nm channel MOSFET transistors [10]. It is based on dc and -parameters measurements.…”

Section: Twa Designmentioning

confidence: 99%

Behavior of a traveling-wave amplifier versus temperature in SOI technology

Moussa

Pavageau

Simon

et al. 2006

IEEE Trans. Microwave Theory Techn.

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In this paper, the design and measurement results of a CMOS partially depleted silicon-on-insulator (SOI) traveling-wave amplifier (TWA) are presented. The four-stage TWA is designed with a single common source nMOSFET in each stage using a 130-nm SOI CMOS technology requiring a chip area of 0.75 mm 2 . A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4-V supply voltage for a power consumption of 66 mW.The designed circuit has been characterized over a temperature range from 25 C to 300 C. The performance degradation on the gain of the TWA, the SOI transistors, as well as the microstrip lines used for the matching network are analyzed. Thanks to the introduction of a dynamic threshold-voltage MOSFET, a greater gain-bandwidth product under lower bias conditions is demonstrated.Index Terms-Dynamic threshold voltage MOSFET (DTMOS), floating body (FB), high-temperature effect, microstrip lines, silicon-on-insulator (SOI), traveling-wave amplifier (TWA).

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A new empirical nonlinear model for sub-250 nm channel MOSFET

Cited by 23 publications

References 7 publications

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

The large world of FET small-signal equivalent circuits (invited paper)

Behavior of a traveling-wave amplifier versus temperature in SOI technology

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