A New Extrinsic Gettering Technique in Thick Bonded Silicon-on-Insulator Wafers Enabling Sensor-Ic Integration

Abstract

A new technique for gettering of transition-metal impurities in thick bonded SOI (BSOI) wafers is demonstrated. A thin poly-Si interlayer was placed between the active silicon layer and the buried oxide by direct wafer bonding. Testing of wafers in CMOS processes showed a clear improvement of the gate oxide integrity, even approaching that of conventional bulk silicon wafers. Poly-Si interlayer layer showed no measurable effects on BSOI characteristics such as bond strength, interfacial voids, or sacrificial oxide etching, and the residual stress was very low. The results suggest that a thin poly-Si layer has minimal effect on fabrication of the MEMS elements.

Gettering in silicon-on-insulator wafers with polysilicon layer

“…The device layer thickness was varied between 10 and 40 m and the buried thermal oxide thickness was about 1000 nm in all wafers. Thermally stable polysilicon layer [9] was deposited by LPCVD (low pressure chemical vapor deposition) using varying growth parameters and layer thicknesses (200-1000 nm). The polysilicon growth parameters in wafer series A were somewhat different than in series B-D. Before iron contamination, all wafers had a bonding anneal at 1100 • C for 2 h. In addition, wafers in series C and D had a high temperature annealing cycle at temperatures above 1000 • C for 24 h. These high-temperature anneals are expected to have an effect on the polysilicon properties such as grain size.…”

“…For instance, deposition of polysilicon on top of the device layer followed by its removal [6,7] and polysilicon trench [8] have been demonstrated to improve the device characteristics in SOI. One possibility is to deposit a polysilicon interlayer between the device layer and BOX [9]. In this approach the gettering feature is built in to the starting material, not to the process itself.…”