A new face down bonding technique using a low melting point metal

Mori, Miki; Saitô, Makoto; Hongu, Akinori; Niitsuma, A.; Ohdaira, H.

doi:10.1109/33.56182

Cited by 13 publications

(2 citation statements)

References 2 publications

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“…The bonding temperature ranges from 165°C to 200°C, and the bonding pressure is between 0.3 MPa and 1.25 MPa. [6][7][8][9] Au/In flip-chip bonding at about 150°C has also been reported, 10 but it is basically controlled by solid-state interdiffusion instead of the liquid-solid reaction of the TLP process.…”

Section: Introductionmentioning

confidence: 99%

Study of the Au/In Reaction for Transient Liquid-Phase Bonding and 3D Chip Stacking

Zhang

Ruythooren

2008

Journal of Elec Materi

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The latest three-dimensional (3D) chip-stacking technology requires the repeated stacking of additional layers without remelting the joints that have been formed at lower levels of the stack. This can be achieved by transient liquid-phase (TLP) bonding whereby intermetallic joints can be formed at a lower temperature and withstand subsequent higher-temperature processes. In order to develop a robust low-temperature Au/In TLP bonding process during which all solder is transformed into intermetallic compounds, we studied the Au/In reaction at different temperatures. It was shown that the formation kinetics of intermetallic compounds is diffusion controlled, and that the activation energy of Au/In reaction is temperature dependent, being 0.46 eV and 0.23 eV for temperatures above and below 150°C, respectively. Moreover, a thin Ti layer between Au and In was found to be an effective diffusion barrier at low temperature, while it did not inhibit joint formation at elevated temperatures during flip-chip bonding. This allowed us to control the intermetallic formation during the distinct stages of the TLP bonding process. In addition, a minimal indium thickness of 0.5 lm is required in order to enable TLP bonding. Finally, Au/In TLP joints of [40 lm to 60 lm were successfully fabricated at 180°C with very small solder volume (1 lm thickness).

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Section: Introductionmentioning

confidence: 99%

Study of the Au/In Reaction for Transient Liquid-Phase Bonding and 3D Chip Stacking

Zhang

Ruythooren

2008

Journal of Elec Materi

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“…Tape-automated bonding (TAB) and chip-on-glass (COG) processes are increasingly used as mounting methods of driver ICs. [1][2][3][4] The driver IC is connected with gold bumps in the TAB or COG proceedure. Accordingly, smoothness of gold bumps has become an important issue to improve the connection reliability between the wiring board and the driver IC on FPDs.…”

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confidence: 99%

Microbump Formation by Noncyanide Gold Electroplating

Watanabe

Hayashi

Honma

1999

J. Electrochem. Soc.

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Formation of gold microbumps by electrodeposition using gold sulfite as a metal source was investigated. Gold bumps 20–80 μm wide and 20 μm high were fabricated by either direct or pulse current plating. It was found that selection of additives in the plating bath is important for the formation of gold bumps having smooth surface without nodules. Soft and uniform gold bumps can be obtained by adding 1–10 ppm of cerium ions in the plating bath. Removal of dissolved air in the plating solution is effective to avoid the skip plating and bubble pinholes on the bumps. Furthermore, higher speed bump formation can be achieved by optimizing the pulse conditions, and the plating rate can be doubled compared with direct current plating. © 1999 The Electrochemical Society. All rights reserved.

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