A new fast rail-to-rail continuous-time common-mode feedback circuit

Mahdavi, Sina; Noruzpur, Faeze; Ghadimi, Esmaii; Khanshan, Tohid Moradi

doi:10.23919/mixdes.2017.8005238

Cited by 3 publications

(2 citation statements)

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“…The reference voltage ideally equals 0 V. Thus, a rectified signal is formed and applied to the fully differential pair, such that, finally, the alteration signal becomes near to zero. The rectified signal is a subtracted value taken by subtracting the reference voltage and the common-mode signal [22,24]. Figure 2 shows the entire architecture of the modified op-amp comparator (GB-CMFD) with gain boosting and common mode current feedback [23][24][25].…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…Section 3 provides details about the simulation results and explanations of the analysis of the modified architecture. Section 4 contains comparisons of the modified architecture with existing op-amp comparators, like DCFIA, SCFIA [19], and CMFD [20][21][22][23], which utilize common mode current feedback through tables and graphs. The paper concludes with Section 5.…”

Section: Introductionmentioning

confidence: 99%

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An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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