A new g&lt;sub&gt;m&lt;/sub&gt;-boosting current reuse CMOS folded cascode LNA

Kargaran, Ehsan; Mafinejad, Yasser; Mafinezhad, Khalil; Nabovati, Hooman

doi:10.1587/elex.10.20130264

Cited by 9 publications

(3 citation statements)

References 8 publications

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“…Given this perspective and the aim of minimizing power usage, various techniques have been explored in the current state of the art. The current-reuse (CR) technique, as documented in [11,12], enables the sharing of the DC current among transistors, thereby reducing power consumption without compromising gain. However, it is important to note that this technique is the most advantageous for applications requiring higher voltage.…”

Section: Introductionmentioning

confidence: 99%

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Subburaman,

Thangaraj,

Balu

et al. 2023

Sensors

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The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than −10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

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Section: Introductionmentioning

confidence: 99%

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Subburaman,

Thangaraj,

Balu

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…Recently, current-reuse has been reported to be very useful design technique for low power LNAs and it was widely used to reduce the overall power consumption and improve the current efficiency. Using this methods, the dc current is shared among transistors, while each contributes to the overall gain of the LNA [3,4,5]. Moreover, Some CMOS-based UWB LNA, which utilize the current-reused technique, were reported [6,7,8,9].…”

Section: Introductionmentioning

confidence: 99%

Design of ultra-wideband LNA with 3.6 ± 0.4 dB NF and 15.9 ± 1.1 dB gain

Pan

Zhang

Huang

et al. 2018

IEICE Electron. Express

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This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) with low and flat noise figure (NF) as well as high and flat gain using 0.18 µm CMOS technology. Frequency range for both NF and gain is expanded by using current-reuse and weak shunt resistor feedback. The LNA consumes 8.4 mW under 1.8 V. High performances are achieved with the gain of 15.9±1.1 dB, NF of 3.6±0.4 dB within 2.9-10.8 GHz band. The input 1 dB compression point (P 1dB ) is -17.1 dBm at 7 GHz. The area of the LNA is 0.63 mm 2 , with pads included.

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“…Current reusing techniques which share the static current of several current-hungry modules, reduce the total power dissipation dramatically [1,2]. However, the inter-module crosstalk cannot be completely avoided in the current reusing structures.…”

Section: Introductionmentioning

confidence: 99%

A 0.6 V passive mixer with high conversion gain in 65 nm CMOS process

Chen

Cai

2015

IEICE Electron. Express

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A passive mixer with a complementary gm stage and a low voltage IF trans-impedance amplifier, which can operate under low voltage conditions, is proposed in this letter. With at most two transistors stacked between vdd and gnd, the proposed mixer can be realized in regular CMOS processes without reducing the threshold voltage of transistors. A high conversion gain is obtained thanks to the high utilization efficiency of the RF current generated by the trans-conductance (gm) stage. A prototype of the proposed mixer structure which works in the frequency band from 1 GHz to 2 GHz is designed and fabricated in SMIC 65 nm CMOS process. Measurement results indicate that, the prototype achieves a conversion of 22 dB and a noise figure of 15 dB. The power consumption is 1.2 mW under the supply voltage of 0.6 V.

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A new g<sub>m</sub>-boosting current reuse CMOS folded cascode LNA

Cited by 9 publications

References 8 publications

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Design of ultra-wideband LNA with 3.6 ± 0.4 dB NF and 15.9 ± 1.1 dB gain

A 0.6 V passive mixer with high conversion gain in 65 nm CMOS process

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