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To ensure qualification of charge-pump locked-loop (CP-PLL), a complete built-in self-test (BIST) scheme should provide functions of measurement of the clock jitter and detection of faults in CP-PLL. This paper proposes a low cost BIST structure providing both the faults detected and timing jitter measured. The structure based on the proposed time-to-digital converter (TDC), which has high resolution and most blocks of TDC are based on the existing blocks in CP-PLL, reduces the test cost and area overhead. The circuit has been designed and simulated in TSMC 0.13 µm CMOS process. The simulation results show that the resolution is about 0.9865 ps and the fault coverage is 98.33%.

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This paper presents a CMOS reference circuit which can work properly under the near-threshold voltage of 0.6 V. It is based on the temperature characteristic of NMOS&PMOS transistors in the sub-threshold region. The temperature curve of the NMOS quasi-PTAT current and the PMOS quasi-PTAT current can be adjusted to have the same slope factor. Thus a temperature-stable reference voltage can be achieved by subtracting the quasi-PTAT voltage generated by the NMOS and PMOS circuits. It can be used under the supply voltage of 0.6 V, under which a traditional bipolarbased band gap reference cannot work properly. The circuit is designed and implemented in SMIC 65 nm CMOS process. It provides a nominal reference voltage of 154 mV, a average temperature coefficient of 87 ppm/°C in [−10°C∼80°C] under a 0.6 V supply voltage. The total power consumption is 60 µW and the chip area is 345 um * 182 um.