A new generation of power lateral and vertical floating islands MOS structures

Morancho, Frédéric; Cézac, N.; Galadi, Abdelghafour; Zitouni, Moaniss; Rossel, P.; Peyre-Lavigne, A.

doi:10.1016/s0026-2692(01)00023-4

Cited by 11 publications

(4 citation statements)

References 6 publications

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“…These are available as commercial products on silicon but only as prototypes on 4H-SiC. Sophisticated silicon structures include alternate P-type and N-type zones in the active layer for getting higher voltage handling (11), so called Mesh-MOS by STM (4), and Cool-MOS by Infineon (6). Bipolar IGBT has very similar structure, but with P+ substrate.…”

Section: Optionnal P-type Inclusionsmentioning

confidence: 99%

(Invited) Perspectives on SiC and III-N Based Devices for Power Electronics

Brylinski¹,

Planson²

2011

ECS Trans.

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SiC devices for power electronics are a reality. A first generation of reliable SiC rectifier devices outperforming all silicon devices has been released on the market with up to 1500V voltage handling capability. At best, GaN based rectifiers, with similar electrical performance and production cost, may reach the market by year 2015. For the same voltage range, prototypes of switching triode SiC devices with control electrode, using JFET and BJT topologies, are also under market evaluation. It seems nobody knows yet whether SiC MOS will finally get reliable enough for voltage over 200 V. III-N based HEMT hetero-junction devices may become superior alternative to the existing SiC switching triode devices. Still, a lot of work will be needed for reaching good enough reliability. On the long term, due to expectable Gallium shortage, SiC based heterojunction devices would offer sustainable solution, although the ideal hetero-structure has not been demonstrated yet.

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Section: Optionnal P-type Inclusionsmentioning

confidence: 99%

(Invited) Perspectives on SiC and III-N Based Devices for Power Electronics

Brylinski¹,

Planson²

2011

ECS Trans.

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“…V br in the area between two adjacent buried oxide layer can be expressed by (2) Where E s is the electric field of the drift region. The electric filed is almost uniform due to the modulation effect of Qs when y <= D], therefore, V br2 enhances by 0.5D]E s in comparison with the conventional PSOI VDMOS.…”

Section: Vdmosmentioning

confidence: 99%

“…The main weakness of this device is that the specific on-resistance (Ron-sp) increases drastically with the increase of the breakdown voltage (V br ) [I] . The floating island MOSFET (FLIMOS) [2][3], oppositely doped buried regions MOSFET [4], power devices with dielectric charge traps [5] , super junction MOSFET [6] and the partial silicon-on-insulator VDMOS (PSOI VDMOS) [7] have been proposed to enhance the V br while keeping a low R on • sr…”

mentioning

confidence: 99%

High figure-of-merit vertical double diffused MOSFET with the charge trenches on partial SOI

Zhang

et al. 2009

2009 Asia Pacific Conference on Postgraduate Research in Microelectronics &Amp; Electronics (PrimeAsia)

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n" substrate L Gate I I E E, dẼ . T (a) (b) n-type Si T E, E L d D E.Fig. I Structure of a TPSO! VDMOS and the trench cell (a) Structure of a TPSO! VDMOS. (b) Trench cell structure and charge distribut ion(M is in the middle of oxide trenches, N is in the comer of oxide trenches, respectively. M and N are in Si). Drain are the thickness, doping concentration and permittivity of the n' drift layer, respectively. D[ is the distance from the bottom of the buried oxide layer to the surface of the TPSOI VDMOS. HI. L[ and 8[ are the height, half of length and permittivity The n-drift region under the p body is divided into three parts. Region I is the silicon on insulator.Region II is the buried oxide layer. Region III is the silicon Abstract-A novel silicon-on-insulator (SOl) high figure-ofmerit vertical double diffused MOSFET (VDMOS) structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOl (TPSOI). The accumulation charges located in the trenches enhance the electric field in the buried oxide layer and uniform the electric field in the drift region, therefore the breakdown voltage (V br ) is enhanced. Simulation shows that the V br and the figure-of-merit of the TPSOI VDMOS increase by 66.8% and 148.1% in comparison with the conventional VDMOS, respectively.

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“…This P buried layer is located under the PsBody/N' plane junction in order to divide, under reverse bias conditions, the maximal electric field into two parts (Fig. 2), allowing the improvement of the breakdown voltage for the same N' epitaxial layer doping concentration [3]. This basically happens due to the fact that the negative charges in the depleted P floating layer tend to terminate a large part of the flux induced by the positive charges of the depleted N' drift region so that the field intensity is not allowed to accumulate throughout the entire thickness of the epitaxial layer, and a larger doping density can be used without producing a high peak field [7].…”

mentioning

confidence: 99%