A new global router based on a flow model and linear assignment

Meixner, G.; Lauther, Ulrich

doi:10.1109/iccad.1990.129836

Cited by 41 publications

(13 citation statements)

References 6 publications

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“…Early sequential routing algorithms include maze-searching approaches [16,21] and line-searching approaches [13], which route net-by-net. Most concurrent algorithms apply network-flow or linear-assignment formulation [1,20] to route a set of nets at one time.…”

Section: Introductionmentioning

confidence: 99%

A novel framework for multilevel routing considering routability and performance

Lin

Chang

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed by uncoarsening. Unlike the previous multilevel routing, we integrate global routing, detailed routing, and resource estimation together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes our framework more flexible in dealing with various routing objectives (such as crosstalk, power, etc). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 3, 0, 3 circuits, respectively. In particular, the number of routing layers used by our router is even smaller. We also have performed experiments on timing-driven routing. The results are also very promising.

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Section: Introductionmentioning

confidence: 99%

A novel framework for multilevel routing considering routability and performance

Lin

Chang

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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“…We have to assign a net to one of four possible slot positions with which the net is passing through the boarder. Our approach uses linear assignment [4,10] to this slot assignment problem. For each net n j and any candidate slot u i , we estimate the cost cost(n j ; u i ) resulting from that assignment.…”

Section: B Phase 2 : Hierarchical Decompositionmentioning

confidence: 99%

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Deguchi

Koide

Wakabayashi

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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Abstract-In the high performance VLSI with multi-layer layout model, the complexity of the global routing problem becomes much high under timing constraints. This paper presents a hierarchical global routing method based on a multi-layer routing model for the high performance standard cell layout. In each hierarchical level, the routes of nets are determined by solving a linear programming problem considering wire-sizing and bufferinsertion under timing constraints. We have implemented the proposed method on a workstation and showed the effectiveness of the method from experimental results. I IntroductionWith recent advances of deep-submicron technologies, VLSI has been used in various kinds of electronics products. Nowadays, the number of transistors mounted on a state-of-the-art VLSI chip is about 108 . In such a VLSI chip, interconnect design plays an important role in determining the chip performance [3], and in recent years, many interconnect optimization techniques, including interconnect wire sizing, driver sizing, buffer insertion and sizing, have been proposed and shown to be very effective for interconnection delay reductions [6,13].As the another concern of the routing process, the routing layers have become more than two. In the past, with one or two layers available for global routing, the job was simply to find the routing channels needed for each net. As the VLSI technologies evolved, the multi-layer (more than two layers) routing makes issues, such as via minimization and layer assignment, much more difficult. In the future, the number of layers of a chip will have more than six or eight [7].In the high performance VLSI with the multi-layer layout model, the complexity of routing problem becomes much high under timing constraints. Although there have been many previous methods for the global routing problem in VLSI layout design, there have been few results on the problem with the multi-layer model. Eugene and Sechen have proposed a multilayer chip-level global router [9], but their layout model is the macro-cell design style. Timing constraints have not also been considered in their method. So, in this paper, we propose a timing-driven hierarchical global routing method with wiresizing and buffer-insertion for a multi-layer channel-less standard cell layout model. To estimate interconnection delay accurately, we adopt the delay estimation model based on Elmore's delay model [8].In the proposed method, we treat a multi-layer model for very large scale circuits and route nets considering both the timing constraints and the routing congestion simultaneously. In the proposed routing method, first, the routing area is divided into sub-regions called blocks. Initially, layout area consists of 424 blocks. Each block at a certain level is divided into 424 recursively. Next, we route nets in each 424 region simultaneously by solving the linear programming problem, in which each possible route of a net is represented as a routing pattern meeting timing constraints considering wire-sizing and buffer-insert...

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“…Early sequential routing algorithms include maze-searching approaches [17], [24] and line-searching approaches [14], which route net-by-net. Most concurrent algorithms apply network-flow or linear-assignment formulation [1], [23] to route a set of nets at one time.…”

Section: Introductionmentioning

confidence: 99%

MR: a new framework for multilevel full-chip routing

Chang

Lin

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose a novel framework for multilevel full-chip routing considering both routability and performance called MR. The two-stage multilevel framework consists of coarsening, followed by uncoarsening. Unlike the previous multilevel routing, MR integrates global routing, detailed routing, and resource estimation, together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes MR more flexible in dealing with various routing objectives (such as crosstalk, power, etc.). Experimental results show that MR obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, MR achieves 100% routing completion for all circuits, while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 2, 0, 2 circuits, respectively. In particular, the number of routing layers used by MR is even smaller. We also have performed experiments on timing-driven routing. The results are also very promising.

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A new global router based on a flow model and linear assignment

Cited by 41 publications

References 6 publications

A novel framework for multilevel routing considering routability and performance

A novel framework for multilevel routing considering routability and performance

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

MR: a new framework for multilevel full-chip routing

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