Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Abstract

Abstract-In the high performance VLSI with multi-layer layout model, the complexity of the global routing problem becomes much high under timing constraints. This paper presents a hierarchical global routing method based on a multi-layer routing model for the high performance standard cell layout. In each hierarchical level, the routes of nets are determined by solving a linear programming problem considering wire-sizing and bufferinsertion under timing constraints. We have implemented the proposed method on a workstation and showed the effectiveness of the method from experimental results. I IntroductionWith recent advances of deep-submicron technologies, VLSI has been used in various kinds of electronics products. Nowadays, the number of transistors mounted on a state-of-the-art VLSI chip is about 108 . In such a VLSI chip, interconnect design plays an important role in determining the chip performance [3], and in recent years, many interconnect optimization techniques, including interconnect wire sizing, driver sizing, buffer insertion and sizing, have been proposed and shown to be very effective for interconnection delay reductions [6,13].As the another concern of the routing process, the routing layers have become more than two. In the past, with one or two layers available for global routing, the job was simply to find the routing channels needed for each net. As the VLSI technologies evolved, the multi-layer (more than two layers) routing makes issues, such as via minimization and layer assignment, much more difficult. In the future, the number of layers of a chip will have more than six or eight [7].In the high performance VLSI with the multi-layer layout model, the complexity of routing problem becomes much high under timing constraints. Although there have been many previous methods for the global routing problem in VLSI layout design, there have been few results on the problem with the multi-layer model. Eugene and Sechen have proposed a multilayer chip-level global router [9], but their layout model is the macro-cell design style. Timing constraints have not also been considered in their method. So, in this paper, we propose a timing-driven hierarchical global routing method with wiresizing and buffer-insertion for a multi-layer channel-less standard cell layout model. To estimate interconnection delay accurately, we adopt the delay estimation model based on Elmore's delay model [8].In the proposed method, we treat a multi-layer model for very large scale circuits and route nets considering both the timing constraints and the routing congestion simultaneously. In the proposed routing method, first, the routing area is divided into sub-regions called blocks. Initially, layout area consists of 424 blocks. Each block at a certain level is divided into 424 recursively. Next, we route nets in each 424 region simultaneously by solving the linear programming problem, in which each possible route of a net is represented as a routing pattern meeting timing constraints considering wire-sizing and buffer-insert...