A new hardware efficient design for the one dimensional discrete Fourier transform

This paper presents a parameterized low power design for the one-dimensional discrete Fourier transform (DFT) of variable lengths.By combining the cyclic convolution formulation, block-based distributed arithmetic, dynamic pipeline technique, and Cooley-Tukey decomposition together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 286 to 4096 points and with different modes of performance, which facilitates the performance-driven design considerations in terms of power consumption and processing speeds. This feature is beneficial to developing a parameterized DFT Intellectual Property (IP) core for meeting the system requirements of different silicon-on-a-chip applications as compared with the existing fixed length DFT designs.

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A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

Guo

Chien

Lin

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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A Star Pattern Recognition Technique Based on the Binary Pattern Formed from the FFT Coefficients

Mehta

Chen

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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A new hardware efficient design for the one dimensional discrete Fourier transform

Cited by 2 publications

References 15 publications

A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

A Star Pattern Recognition Technique Based on the Binary Pattern Formed from the FFT Coefficients

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