A new hardware realization of digital filters

Peled, A.; Liu, Bede

doi:10.1109/tassp.1974.1162619

Cited by 450 publications

(101 citation statements)

References 8 publications

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“…ASIC based Implementation of FIR Filter provides little costlier and long development time but gives high flexibility. The realization of FIR filter based on FPGA received extensive attention because it gives high flexibility, high performance, low cost and shorter development time [8]. The core of the FIR filter implementation is multiplication and accumulation (MAC) operation.…”

Section: Fpga Implementation Using Various Algorithmsmentioning

confidence: 99%

“…Distributed Arithmetic is a famous method, which converts calculation of MAC to a serial of look up table accesses and summation [8]. It was initially proposed by Croisier in 1973 [7] and further developed by Peled and Lui [8].The principle of DA algorithm is as follows:…”

Section: A Distributed Arithmetic and Da-obcmentioning

confidence: 99%

“…It was initially proposed by Croisier in 1973 [7] and further developed by Peled and Lui [8].The principle of DA algorithm is as follows:…”

Section: A Distributed Arithmetic and Da-obcmentioning

confidence: 99%

See 2 more Smart Citations

FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

Dhobi¹,

Shukla²,

Bhatt³

2014

International Journal of Research in Computer Science

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Section: Fpga Implementation Using Various Algorithmsmentioning

confidence: 99%

Section: A Distributed Arithmetic and Da-obcmentioning

confidence: 99%

See 1 more Smart Citation

FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

Dhobi¹,

Shukla²,

Bhatt³

2014

International Journal of Research in Computer Science

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“…A few largest singular values of H 2 can be used to approximately represent it as H2 by singular value decomposition(SV D) [7]. Further reduction in complexity can be achieved by LU decomposition on H 2 to realize it as R number of FIR filters, followed by squarers, where R is the rank of H 2 which can be considerably less than N. Also, realizations which distribute multiplications and additions at the bit level are possible for quadratic filters [8], [9 ].…”

Section: Discrete Volterra Seriesmentioning

confidence: 99%

Quadratic predictor based differential encoding and decoding of speech signals

Hari¹,

Raj

Gopikakumari

2011

2011 International Conference on Communications and Signal Processing

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Abstract-Modeling nonlinear systems using Volterra series is a century old method but practical realizations were hampered by inadequate hardware to handle the increased computational com plexity stemming from its use. But interest is renewed recently, in designing and implementing filters which can model much of the polynomial nonlinearities inherent in practical systems.The key advantage in resorting to Volterra power series for this purpose is that nonlinear filters so designed can be made to

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“…Peled and Liu [3] outlined an approach to the implementation of one-dimensional recursive digital filter structures described by distributed arithmetic. This realization requires storing the finite number of possible outcomes of an arithmetic operation, as well as using them to obtain the next output sample through repeated additions and Manuscript received March 22, 1982; revised May 8, 1985.…”

Section: Introductionmentioning

confidence: 99%

Real-time image processing by distributed arithmetic implementation of two-dimensional digital filters

Jaggernauth

Loui²,

Venetsanopoulos³

1985

IEEE Trans. Acoust., Speech, Signal Process.

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Abstract-This paper describes the implementation of two-dimensional recursive digital filters for real-time image processing. The filter structure is described by distributed arithmetic and the operations involved are memory fetches and additions. An error analysis of the twodimensional filter structure described by distributed arithmetic is outlined and the expression for the mean-squared error is derived. This approach is compared to an equivalent conventional filter structure using multipliers. It is demonstrated that the distributed arithmetic implementation offers a significant reduction in cost as well as power consumption for real-time image processing. In addition, the hardware design of a second-order two-dimensional distributed filter is presented and its performance is examined. This filter is constructed using standard integrated circuits and memories and is capable of filtering images of sizes up to 256 X 256 pixels in real time.

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A new hardware realization of digital filters

Cited by 450 publications

References 8 publications

FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

Quadratic predictor based differential encoding and decoding of speech signals

Real-time image processing by distributed arithmetic implementation of two-dimensional digital filters

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