1985
DOI: 10.1109/tassp.1985.1164739
|View full text |Cite
|
Sign up to set email alerts
|

Real-time image processing by distributed arithmetic implementation of two-dimensional digital filters

Abstract: Abstract-This paper describes the implementation of two-dimensional recursive digital filters for real-time image processing. The filter structure is described by distributed arithmetic and the operations involved are memory fetches and additions. An error analysis of the twodimensional filter structure described by distributed arithmetic is outlined and the expression for the mean-squared error is derived. This approach is compared to an equivalent conventional filter structure using multipliers. It is demons… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

1989
1989
1998
1998

Publication Types

Select...
3
2
1

Relationship

0
6

Authors

Journals

citations
Cited by 33 publications
(2 citation statements)
references
References 11 publications
0
2
0
Order By: Relevance
“…EMPPM improves the noise margin compared with MPPM by using the 2-bit SAD and 4-level quantization. Although EMPPM is not as robust against noise as the direct-form architectures [4,5], the proposed architecture can dramatically reduce the gate count compared with those in [4,5] due to :?-bit SAD operations instead of 8-bit SAD. In addition, EMPPM can reduce the gatle count about 28% compared with the MPPM architecture [3].…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…EMPPM improves the noise margin compared with MPPM by using the 2-bit SAD and 4-level quantization. Although EMPPM is not as robust against noise as the direct-form architectures [4,5], the proposed architecture can dramatically reduce the gate count compared with those in [4,5] due to :?-bit SAD operations instead of 8-bit SAD. In addition, EMPPM can reduce the gatle count about 28% compared with the MPPM architecture [3].…”
Section: Discussionmentioning
confidence: 99%
“…For gate count comparisons, we assume that the size of template image is 4x4 and consider the architectures only consisting of a PE Array and Adder Trees without having a Shift Register Array and a control unit. The direct form architectures [4,5] use the 8-bit SAD without preprocessing. Their processing times are slower than other architectures due to the critical path of 8-bit SAD operations.…”
Section: Implementation and Com[parisons With Existing Architecturesmentioning
confidence: 99%