A new lateral power MOSFET for smart power ICs: the “LUDMOS concept”

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

“…Though there are many researches addressed on 1-D breakdown behavior [5]- [7], still there are few works deal with a 2-D breakdown model. The STI has been used in DEMOS transistor to enhance the breakdown voltage (BV) by increasing the length of the drain extension region without sacrificing the device area [8]. Besides, the field plate can be used to enhance the device BV by controlling the curvature of depletion layer [9]- [11].…”

NBTI degradation in STI-based LDMOSFETs

“…With the advantage of the process compatibility with the mainstream standard Complementary Metal Oxide Semiconductor (CMOS), with an insertion of shallow-trench-isolation (STI) region in LDMOS devices, STI-based laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET), have become popular for their better tradeoff between breakdown voltage and performance [1]. Due to the capability of handling high voltage and high current levels, reliability of power devices is of prime importance, most of hot-carrier-injection (HCI) studies are focused on nLDMOSFETs rather than pLDMOSFETs [2][3][4].…”

High-voltage SOI lateral MOSFET with a dual vertical field plate

“…In order to improve the R on,sp characteristic while maintaining a high BV, the trench technologies are used in the fabrication of power lateral MOSFETs. [1][2][3][4][5][6] By implanting the oxide trench in the drift region, the power lateral MOSFETs can achieve reduced R on,sp because of the shortened cell pitch. [7][8][9] A two-dimensional analytical model is then developed to explore the physical mechanism of the oxide trench in the silicon-on-insulator (SOI) trench lateral MOSFETs.…”