A new low-voltage full adder circuit

Lee, H.; Sobelman, Gerald E.

doi:10.1109/glsv.1997.580416

Cited by 26 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When the power-supply voltage is reduced, other factors may play a role in changing the ranking of the adder cells. For example, having incomplete voltage swing at some internal nodes may lead to a constant current drain, which in turn increases the power consumption of the cell than usual [11].…”

Section: First Circuit Structure Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Performance analysis of low-power 1-bit CMOS full adder cells

Shams

Darwish

Bayoumi

2002

IEEE Trans. VLSI Syst.

409

154

View full text Add to dashboard Cite

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

show abstract

Section: First Circuit Structure Simulation Resultsmentioning

confidence: 99%

“…Each adder exhibits its own figures for power consumption, delay, area, and driving capability. The transistor count for adders used in this paper is much less than the ones used in [11], which range from 24-48 transistors and the ones used in [12], which range from 26-54 transistors.…”

Section: Building the 1-bit Full Adder Cellsmentioning

confidence: 99%

Performance analysis of low-power 1-bit CMOS full adder cells

Shams

Darwish

Bayoumi

2002

IEEE Trans. VLSI Syst.

409

154

View full text Add to dashboard Cite

show abstract

“…Dynamic power constitutes the majority of the power dissipated in CMOS circuits. It is the power dissipated during charging or discharging the load capacitances of a given circuit [6]. It depends on the input pattern that will either cause the transistors to switch (consume dynamic power) or not to switch (no dynamic power consumed) at every clock cycle.…”

Section: Source Of Power Consumptionmentioning

confidence: 99%

Novel High-Efficient Full Adder Cell Based on Bootstrapped Structure

Cheng¹,

Hu²

2014

IJAST

View full text Add to dashboard Cite

show abstract

“…Any changes cannot be made to an and-gate which itself is the most basic structure. So, here in this project; Adders which are made up of xor and xnor gates are concentrated on, which can be modified [4].…”

Section: Introductionmentioning

confidence: 99%

Design of Wallace tree multiplier circuit using high performance and low power full adder

Leela,

Manisha,

Bharath

et al. 2023

E3S Web Conf.

View full text Add to dashboard Cite

The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.

show abstract

A new low-voltage full adder circuit

Cited by 26 publications

References 5 publications

Performance analysis of low-power 1-bit CMOS full adder cells

Performance analysis of low-power 1-bit CMOS full adder cells

Novel High-Efficient Full Adder Cell Based on Bootstrapped Structure

Design of Wallace tree multiplier circuit using high performance and low power full adder

Contact Info

Product

Resources

About