A new LP based incremental timing driven placement for high performance designs

Abstract

In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advantage of the path-based delay sensitivity with limited-stage slew propagation, thus it enjoys certain hybrid feature of net and path-based timing driven placement. Our LP formulation considers not only cells on the critical paths, but also cells that are logically adjacent to the critical paths (i.e., the criticality ad jacency network) in a unified manner. We further present a timing aware spreading method to preserve timing in legalization for high performance designs. Our algorithm has been tested on a set of 65nm industry circuits from a multi-GHz microprocessor, and shown to achieve much improved timing on hand-tuned circuits.

Path smoothing via discrete optimization

“…Since our transform can be enacted by any high-level driver, we are free to assume that an external mechanism chooses individual gates for relocation (e.g., such as all imbalanced latches [18]). In expanding the movable logic to include additional gates, various heuristics have been proposed that incorporate the degree of neighbors' criticality [22,14]. We combine the criticality adjacency network of [14] with an N -hop neighborhood, in which any gate within N steps of the targeted gate is included in the set of movable cells; however, we stress that our core timing-driven placement engine can be parameterized with any well-formed gate-selection strategy.…”

“…In expanding the movable logic to include additional gates, various heuristics have been proposed that incorporate the degree of neighbors' criticality [22,14]. We combine the criticality adjacency network of [14] with an N -hop neighborhood, in which any gate within N steps of the targeted gate is included in the set of movable cells; however, we stress that our core timing-driven placement engine can be parameterized with any well-formed gate-selection strategy. All peripheral gates connected to movable logic form a set of fixed nodes.…”

“…A piecewise-linear approximation of the quadratic function is employed by Chowdhary et al [7], along with additional constraints to capture net length and load capacitance using differential timing analysis. Luo et al [14] optimize a weighted slack objective in which Elmore delays computed from the original placement are scaled linearly by a coefficient; to ensure that gates are not displaced by extremely large distances, movement of individual cells is constrained by bounding boxes, similar to the approach taken by Halpin et al [10]. Most recently, Papa et al [18] deploy an LP formulation in late stages of refinement after stripping all repeaters out from combinational logic and subsequently re-buffering long wires as a post-processing step.…”

Pyramids: An efficient computational geometry-based approach for timing-driven placement

“…The delay on an optimally buffered long net is approximately linearly proportional to its length [11,12]. The traditional approach for timing optimization is to use a linear delay model for gates to calculate the circuit delay [4,5,6,7,8]. Static timing analysis is used to create linear programs that model the timing objective and a linear programming solver is used to generate an optimal location for each cell.…”

“…Timing-driven global placement commonly uses netweighting and net-constraints based methods to address timing [1,2,3], but they are again inadequate to solve the problem completely. Thus there is a body of work mostly using mathematical programming to incrementally improve circuit timing [4,5,6,7,8]. Mathematical programming based approaches can be expensive to solve.…”