A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs

Lee, R.G.-H.; Su, Jen-Yi; Chung, Steve S.

doi:10.1109/16.477596

Cited by 44 publications

(23 citation statements)

References 13 publications

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“…In the second case, the pulse base is fixed in accumulation ( V) and the pulse top is varied. The pulse scans the local threshold voltage ( ) distribution and the resulting -data are recorded (details of the gate pulsing scheme can be found in [23] and [25]). Prestress measurements are performed on transistors having different drawn gate length ( ).…”

Section: Experimental Techniquementioning

confidence: 99%

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Mahapatra

Parikh

Rao

et al. 2000

IEEE Trans. Electron Devices

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Abstract-The influence of channel length and oxide thickness on the hot-carrier induced interface () and oxide ( ) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate and profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The and profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.Index Terms-Channel length and oxide thickness dependence, charge pumping, hot-carrier effect, MOSFET, spatial profiling of damage.

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Section: Experimental Techniquementioning

confidence: 99%

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Mahapatra

Parikh

Rao

et al. 2000

IEEE Trans. Electron Devices

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“…The simulation based methods [4]- [8] employ a source/drain reverse bias [4]- [6] or a variable amplitude gate pulse [7], [8] to vary the CP area and depend heavily on device simulations to determine damage position. These methods are unsatisfactory due to the requirement of exact device structure and doping profiles.…”

mentioning

confidence: 99%

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

Mahapatra

Parikh

Rao

et al. 2000

IEEE Trans. Electron Devices

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Abstract-A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface ( ) and oxide ( ) traps in hot-carrier stressed MOSFET's. Direct separation of and is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation, and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms.Index Terms-Charge pumping, hot-carrier effect, MOSFET, spatial damage profiles.

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“…However, in deep submicron scale, the hot-carrier induced damage becomes a major reliability concern. These hot-carriers result from the impact of ionization in the channel near the drain junction, which subsequently are injected into the gate oxide and give rise to a localized and non-uniform pileup of interface states and oxide charges near the drain-channel junction [4,5]. The hot-carrier related device instabilities have become a major reliability concern in modern CMOS-based devices and are expected to get worse in future generation of devices.…”

mentioning

confidence: 99%

“…The main cause of the hot-carrier degradation effect in the conventional bulk MOSFETs is already discussed in many Refs. [4][5][6]. Recently, F. Djeffal et al [1] have proposed a new closed analytical model to study the multigate MOSFETs including the interfacial hot-carrier effects in order to investigate the scaling limits of these devices when defects generated by channel hot-carrier are present.…”

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confidence: 99%

An analytical drain current model for undoped GSDG MOSFETs including interfacial hot‐carrier effects

Djeffal¹,

Bentrcia²,

Bendib³

2010

Phys. Status Solidi (c)

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In the present work, a comprehensive drain current model including the interfacial hot‐carrier degradation effects for undoped symmetric gate stack double gate (GSDG) MOSFET and the expressions of transconductance and drain conductance have been obtained. Exploiting this new device model, we have found that the incorporation of a high‐k layer between oxide region and gate metal leads to drain current enhancement, improved output conductance, increased transconductance parameter and enhanced interfacial hot‐carrier immunity. The proposed model has been validated by comparing the analytical I‐V characteristics with 2‐D numerical results. The obtained results may provide a theoretical basis and physical insights for multigate MOSFET‐based circuits design including the hot‐carrier degradation effects. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs

Cited by 44 publications

References 13 publications

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

An analytical drain current model for undoped GSDG MOSFETs including interfacial hot‐carrier effects

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