A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

Chaharmahali, Iman; Asadi, Sareh; Dorostkar, B.; bosra, Mosa malaknezhad; Abedini, Moein

doi:10.1007/s10470-017-1026-z

Cited by 5 publications

(2 citation statements)

References 21 publications

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“…We know that over the past years, because of technology advancements, the supply voltage has undergone major reduction without any significant intervention on threshold voltage. So cascode structures are not compatible with low‐supply voltages and submicron fabrication, while multistage structures provide high direct current (DC) gain easily . We also know that a multistage amplifier with frequency compensation network is immensely complicated and that everything is in some way connected.…”

Section: Introductionmentioning

confidence: 99%

“…So cascode structures are not compatible with low-supply voltages and submicron fabrication, while multistage structures provide high direct current (DC) gain easily. [10][11][12][13][14][15][16] We also know that a multistage amplifier with frequency compensation network is immensely complicated and that everything is in some way connected. Additionally, because of design simplicity, many assumptions are considered to more simple statements.…”

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confidence: 99%

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A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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Enhanced comparator‐based switched‐capacitor integrator using current conveyor

Chaharmahali

Mianvelayat²,

Biabanifard³

2020

Int J Numerical Modelling

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New schematic for comparator‐based switched‐capacitor (CBSC) integrator is proposed. In comparison with conventional CBSC integrators, the presented circuit helps to reduce significantly the power consumption while improving the signal‐to‐noise ratio (SNR) and the defined figure of merit (FOM). This was obtained by using a second‐generation current conveyor (CCII) in charge scheme. The integrator design is based on the 0.18‐μm CMOS technology with a frequency of 5 MHz; the proposed first‐order CBSC integrator exhibits 22.87 dB as SNR and 60 μW as power dissipation at 1.8‐V supply voltage.

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