2013
DOI: 10.1088/1674-1137/37/11/116102
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A new method of waveform digitization based on time-interleaved A/D conversion

Abstract: Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limitation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit 1-Gsps waveform digitizer … Show more

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Cited by 6 publications
(5 citation statements)
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References 28 publications
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“…The External-target Experiment (CEE) at the HIRFL-CSR will be a large-scale GeV nuclear physics experiment independently developed in China. The Zero-degree calorimeter [453] uses is a 16-channel, 14-bit pipeline ADC (AD9249) [454] with a sampling rate of 65 MHz to realize waveform digitization. For the MAPS in heavy-ion physics, a regional 12-bit 40-Msps pipeline ADC has been designed to convert the analog signals from the pixels into digital data [455].…”
Section: Waveform Digitizationmentioning
confidence: 99%
“…The External-target Experiment (CEE) at the HIRFL-CSR will be a large-scale GeV nuclear physics experiment independently developed in China. The Zero-degree calorimeter [453] uses is a 16-channel, 14-bit pipeline ADC (AD9249) [454] with a sampling rate of 65 MHz to realize waveform digitization. For the MAPS in heavy-ion physics, a regional 12-bit 40-Msps pipeline ADC has been designed to convert the analog signals from the pixels into digital data [455].…”
Section: Waveform Digitizationmentioning
confidence: 99%
“…One possible solution is to employ two channels with sampling clocks of 180° phase shift to achieve time interleaved modulation. By this method, the sampling rate will be doubled but a correction mechanism is needed to correct the gain, phase and offset difference between the channels [44].…”
Section: ) Time Interleaved Fpga-adcmentioning
confidence: 99%
“…The output signal from A3 is digitized by the 12-bits 62.5-Msps ADC. The time measurement is based on the leading edge discrimination and the FPGA (Field Programmable Gate Array)-based TDC technique [16,[24][25][26][27][28][29]. In order to extract the charge information, the output data stream of the ADC was fed to the FPGA for peak detection or waveform integration.…”
Section: A Charge Measurement In the Lhaaso Wcda Faementioning
confidence: 99%