A New Method to Extract EOT of Ultrathin Gate Dielectric With High Leakage Current

Luo, Zhijiong; Ma, T.P.

doi:10.1109/led.2004.834634

Cited by 40 publications

(24 citation statements)

References 4 publications

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“…Analytic solutions of such models are considered in [20]- [24], but the general solution method for such models is the numerical solution. A MOS equivalent capacitance determination algorithm was written for the Agilent B1500A, which utilizes highfrequency measurements and 3-element model calculated from the 2-element model extracted from the experimental data.…”

Section: Measurement Methodsmentioning

confidence: 99%

Automatic Parameter Extraction Technique for MOS Structures by C-V Characterization Including the Effects of Interface States

Ryazantsev

Grudtsov

2016

Measurement Science Review

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A large number of methods exist for the extraction of parameters and calculation of C-V characteristics that account for quantum effects [5]. These methods are based on the calculation of C-V characteristics for each set of parameters. In other works, [6], [7], a statistical approach is suggested, which is based on the comparison of the experimental curve to a database created in advance. This can work for silicon-on-insulator (SOI) structures as well as bulk substrate. The usage of a database containing the selfconsistent solutions of Schrodinger-Poisson equations can decrease the modeling time noticeably. However, the and Manufacturing Complex "Technological Center", Georgievsky prospect 5, 124498, Zelenograd, Moscow, Russia, V.Grudtsov@tcen.ru An automatic MOS structure parameter extraction algorithm accounting for quantum effects has been developed and applied in the semiconductor device analyzer Agilent B1500A. Parameter extraction is based on matching the experimental C-V data with numerical modeling results. The algorithm is used to extract the parameters of test MOS structures with ultrathin gate dielectrics. The applicability of the algorithm for the determination of distribution function of DOS and finding the donor defect level in silicon is shown.

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Section: Measurement Methodsmentioning

confidence: 99%

Automatic Parameter Extraction Technique for MOS Structures by C-V Characterization Including the Effects of Interface States

Ryazantsev

Grudtsov

2016

Measurement Science Review

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“…As a result, only an inversion C-V analysis can be performed on FinFETs, unless other dedicated test structures are utilized. Also, many of the methodologies that are commonly used in planar bulk MOSFETs for accurately measuring the gate C-V are based on the C-V analysis in the accumulation region, and hence are inapplicable to FinFETs [18], [19]. Therefore, to accurately measure the C-V characteristics of FinFETs, special test structures are designed, as is shown in Fig.…”

Section: Test Structures and Device Fabricationmentioning

confidence: 99%

Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Dixit

Bandhyopadhyay

Collaert

et al. 2009

2009 22nd International Conference on VLSI Design

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FinFET is one of the promising device architectures for sub-32nm CMOS technology nodes. These nonplanar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help evaluate the circuit potential of FinFETs by experimentally comparing their parasitic capacitance to that of the planar FDSOI MOSFETs. It is shown that n-and p-channel FinFETs achieve as high as 50% and 28% parasitic capacitance reduction compared to the planar FDSOI MOSFETs respectively.

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“…This experiment unambiguously demonstrates that the major part of frequency dispersion on non-ideal oxide/III-V material interface does relate to the interface properties instead of simple parasite effect, which can be corrected by twofrequency correction or multi circuit element models. (21)(22) The dielectric constant is ~ 8.1 deduced from the measured C max , the area of the capacitor and the film thickness. For annealed 16nm Al 2 O 3 /GaAs, the average frequency dispersion of accumulation capacitance is 8% per decade due to mentioned ashing process and bulk property degradation.…”

Section: Ecs Transactions 3 (3) 59-69 (2006)mentioning

confidence: 99%

Capacitance-Voltage Characterization of Atomic-Layer-Deposited Al2O3/InGaAs and Al2O3/GaAs Metal-Oxide-Semiconductor Structures

Xuan

Lin

2006

ECS Trans.

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In 0.2 Ga 0.8 As MOS and sourcedrain implanted MOSFET structure were fabricated and characterized by capacitance-voltage (C-V) and current-voltage (I-V) measurements. It is shown that, after high-temperature anneal, the MOS leakage current density of the thinner (16nm) film is much higher than that of the thicker (30nm) film. The high-quality Al 2 O 3 (30nm)/In 0.2 Ga 0.8 As interface after high temperature anneal is verified by C-V curves showing sharp transition from depletion to accumulation with "zero" hysteresis, 1% frequency dispersion per decade at accumulation capacitance and strong inversion under split C-V measurement. However, Al 2 O 3 (16nm)/GaAs shows larger hysteresis and frequency dispersion with no inversion layer formed under split C-V measurement. Photo-assisted C-V measurement shows the inversion layer easily formed on In 0.2 Ga 0.8 As interface but not on GaAs interface, indicating higher surface recombination rate at GaAs interface. The estimated interface trap density (D it ) by split C-V method shows 2.9×10 11 /cm 2 -eV for Al 2 O 3 /In 0.2 Ga 0.8 As. Minority-carrier response of Al 2 O 3 /In 0.2 Ga 0.8 As and Al 2 O 3 /GaAs is systematically studied by high-temperature C-V measurements which reveal the activation energy (E A ) of the minority-carrier recombination to be about 0.62 ± 0.03 eV for InGaAs and 0.71 ± 0.01 eV for GaAs, respectively.

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A New Method to Extract EOT of Ultrathin Gate Dielectric With High Leakage Current

Cited by 40 publications

References 4 publications

Automatic Parameter Extraction Technique for MOS Structures by C-V Characterization Including the Effects of Interface States

Automatic Parameter Extraction Technique for MOS Structures by C-V Characterization Including the Effects of Interface States

Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Capacitance-Voltage Characterization of Atomic-Layer-Deposited Al2O3/InGaAs and Al2O3/GaAs Metal-Oxide-Semiconductor Structures

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