A new methodology for improved tester utilization

Khoche, A.; Kapur, R.; Armstrong, D.; Williams, T.W.; Tegethoff, M.M.V.; Rivoir, Jochen

doi:10.1109/test.2001.966715

Cited by 16 publications

(7 citation statements)

References 5 publications

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“…Some of the earliest work in this area was described in [5], [6] and [7] in the context of efficiently partitioning test resources between ATE electronics and on-chip DFT structures. ATE can transfer test data at 5-20X faster than typical scan shift frequencies, but are pin-limited due to the high cost of high-speed test pins.…”

Section: Previous Workmentioning

confidence: 99%

SmartScan - Hierarchical test compression for pin-limited low power designs

Chakravadhanula

Chickermane

Pearl

et al. 2013

2013 IEEE International Test Conference (ITC)

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IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

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Section: Previous Workmentioning

confidence: 99%

SmartScan - Hierarchical test compression for pin-limited low power designs

Chakravadhanula

Chickermane

Pearl

et al. 2013

2013 IEEE International Test Conference (ITC)

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“…One goal of ordering test patterns according to fault/defect coverage is to detect defects earlier so as to save test application time when using the abort-on-fail technique. However, as multisite testing strategy [11,12,13,14] (which is a method to test multiple copies of the same circuit in parallel on one test equipment) is increasingly adopted, the savings in time offered by the early defect detection diminishes because the entire test set needs to be applied to the end as long as there is one device under test that is defect free. The experimental results in [15] show that the abort-on-fail technique has rather limited benefits when used in combination with multi-site testing.…”

Section: Prior Workmentioning

confidence: 99%

A test pattern ordering algorithm for diagnosis with truncated fail data

Chen

Reddy

Pomeranz³

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method.

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“…Two such extensions are re-configurable RPCT [4] and Enhanced RPCT [9]. In [4], a technique to design an RPCT wrapper around an SOC is presented. In this case, the DfT for the SOC can be designed without even knowing about the target ATE.…”

Section: Prior Workmentioning

confidence: 99%

“…The other way to increase the number of sites is to narrow down the SOC-ATE interface, i.e., the number of SOC terminals that needs to be contacted during testing. Reduced-Pin-Count-Test (RPCT) [8,9,4] is a well-known DfT technique that does exactly this. This paper focuses on designing and optimizing an on-chip test infrastructure (DfT) to facilitate high-throughput multi-site wafer testing of large SOCs.…”

Section: Introductionmentioning

confidence: 99%