SmartScan - Hierarchical test compression for pin-limited low power designs

Abstract

IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

“…Some examples are low pin count test with TestKompress [2], [5], [17], Version G2 of adaptive scan in DFTMAX from Synopsys [4] and SmartScan in Encounter DFT from Cadence [1]. A detailed analysis shows [9] how RPCT improves fault coverage of test compression so that test time and test size are greatly reduced through elimination of extra top off patterns.…”

“…In compression-based testing, RPCT using serialization/deserialization can significantly reduce test time and test size [9]. If we send test data with MVL-compatible test channel, boosting data rate by several times, then the benefit of RPCT can be further enhanced.…”

“…This ratio is determined by how many bits need to be deserialized. As often stated [9], [15], [21], this technique is claimed to solve the bandwidth mismatch between the fast ATE channel and slow DUT scan speed. However, this will become a speed bottleneck for RPCT in circumstances when the ATE channel speed cannot keep pace with the DUT scan speed times number of serialized bits.…”

“…Two major test compression categories are linear-decompressionbased scheme and broadcast-scan-based scheme [22], where compression effectiveness is related to the ratio between the number of inner scan chains and decompressor input channels. However, the compression algorithms [9] do not allow too few decompressor input channels in which case the fault coverage may degrade because of the correlation problem.…”

“…To reduce the number of test pins, RPCT has been proposed [9]. A practical RPCT interface is shown in Figure 1.…”