A New Paradigm for FPGA Placement Without Explicit Packing

Li, Wuxi; Pan, David Z.

doi:10.1109/tcad.2018.2877017

Cited by 24 publications

(12 citation statements)

References 26 publications

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“…At the moment, we do not have a sound method for legalizing the number of inputs to each cluster, so we increase the number of physical cluster inputs to 60 for both architectures (the maximum for a ten 6-LUT cluster). As this is not uncommon in industrial architectures [10,17], we do not believe that it has any impact on the validity of the results.…”

Section: Methodsmentioning

confidence: 86%

“…Treating individual LUTs as movable objects during placement can result in superior placement quality [3] and some modern placement algorithms demonstrate that this is practicable at scale [17]. However, a typical FPGA CAD low includes a packing stage before the actual placement [1], which groups LUTs together so that each group can be implemented by a logic cluster of the FPGA.…”

Section: Necessity Of Placing Individual Lutsmentioning

confidence: 99%

“…Node 14 must also be kept, as it informs the solver that there is an alternative path between nodes 11 and 18, which may at some point become the determining factor for the arrival time of node 18. If that happens, no more efort should be spent on trying to further decrease this arrival time, by decreasing the delay of edge (15,17). Instead, an attempt to optimize other edges should be made.…”

Section: Delay-based Model Compactionmentioning

confidence: 99%

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Nikolić

Zgheib

Ienne

2022

ACM Trans. Reconfigurable Technol. Syst.

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In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer which moves a carefully selected subset of LUTs from their original positions, so that connections of the user circuit can be appropriately aligned with the direct connections of the FPGA, reducing the circuit’s critical path delay. We discuss various aspects of making such an approach practicable, from efficient formulation of the integer programs themselves, to appropriate selection of the movable nodes. These careful considerations enable simultaneous movement of tens of LUTs with tens of candidate positions each, in a matter of minutes. In this manner, the impact of additional connections on the critical path delay more than doubles, compared to the previously reported results that relied solely on architecture-oblivious placement.

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Section: Methodsmentioning

confidence: 86%

Section: Necessity Of Placing Individual Lutsmentioning

confidence: 99%

Section: Delay-based Model Compactionmentioning

confidence: 99%

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Nikolić

Zgheib

Ienne

2022

ACM Trans. Reconfigurable Technol. Syst.

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“…(1.4) Resource Demand/Supply Adjustment: Based on the packing feasibility and routing congestion level, the area demand of some standard cells like LUTs and FFs will shrink or increase and the area supply of some regions will be increased or reduced, to improve the placement quality. This phase is adopted from extended UTPlaceF [38].…”

Section: B Problem Formulationmentioning

confidence: 99%

“…As mentioned in Section I-A, analytical placers approximate the wirelength (or HPWL) and some other metrics in numerical models for efficient solutions. Like what many previous analytical placers [6] [8] [9] [43] [38], to approximate the underivable HPWL function,…”

Section: B Timing-driven Quadratic Placementmentioning

confidence: 99%

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

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To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

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Physical Implementation

Tu,

Tang,

et al. 2024

Fpga Eda

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A New Paradigm for FPGA Placement Without Explicit Packing

Cited by 24 publications

References 26 publications

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Physical Implementation

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