A new parallel prefix adder structure with efficient critical delay path and gradded bits efficiency in CMOS 90nm technology

Moqadasi, H.; Ghaznavi‐Ghoushchi, M. B.

doi:10.1109/iraniancee.2015.7146426

Cited by 4 publications

(1 citation statement)

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“…But the above existing 32 bit basic carry adders having high delay value in higher order bits because each level of adder has to wait for the previous carry result [3]. Due to the above problem of 32 bit basic existing carry adders, in today's world of technology, PPA is well suitable designed adder for high speed addition process with less delay in VLSI technology [4]. Also the PPA is one of the most popular designs and provides good negotiation amongst area, speed and power [5].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Daphni¹,

Grace²

2019

Adv. sci. technol. eng. syst. j.

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The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.

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Section: Introductionmentioning

confidence: 99%