The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.
Abstract-Noise reduction of speech signals is a key challenge problem in speech enhancement, speech recognition and speech communication applications, etc. It has attracted a considerable amount of research attention over past several decades. The most widely used method is optimal linear filtering method, which achieves clean speech estimate by passing the noise observation through an optimal filter or transformation. Most common problem in speech processing is the effect of interference noise in speech signals, Interference noise masks of the speech signal and reduces its Intelligibility. It is necessary to remove the noise from the speech signals to get the clear understanding of the information that the speech signal contains. Normally, LMS adaptive filter is used for the process of noise removal in the speech signals. The Direct Form LMS adaptive filter is the most popular and most widely used adaptive filter, not only because of its simplicity but also because of its satisfactory convergence performance. In order to achieve the above mentioned objective, the concept of adaptive filtering algorithm is to be used. This algorithm is developed using MATLAB version 7.8.0.347(R2009a) and Xilinx 9.1 MSE, the comparison is done with LMS and NLMS Algorithms.
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