A review analysis of parallel prefix adders for better performnce in VLSI applications

Daphni, S; Grace, K. S. Vijula

doi:10.1109/iccs1.2017.8325971

Cited by 18 publications

(5 citation statements)

References 7 publications

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“…Basically a simple half adder and full adder are used for constructing the complex adders like CLA, CSA and RCA [16]. The intermediate propagate and generate signals are formed in the complex adders [17].…”

Section: Carry Propagate-generate Techniquementioning

confidence: 99%

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Shanmugam¹,

Kumar²

2022

Preprint

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Ternary adders have produced more benefits compared to the binary adders (i.e.) the ternary adder occupies less amount of area as well as produces less interconnect complexity. But the CMOS implementation of the ternary adders are failed to perform the process when the channel length is taken as 32nm. At 32nm technology, the CMOS transistors are exhibited undesired effects such as SCE, mobility degradation, etc., These issues are overcome by multi-gate devices. CNFETs (Carbon Nano-tube Field Effect Transistors) are the one of the technology to work efficiently when channel length is 32nm. In this paper, CNFETs based ternary prefix adders are designed. The power consumption is the most needed requirement for the VLSI system. So, this can be achieved by reducing the number of transistors. The reduction approach is called as the GDI (Gate Diffusion Input) logic is also included in the proposed prefix adder design. The proposed adder improved by reducing the power upto 83%, Energy upto 83%, current upto 78%, delay upto 96%. Finally, the PDP (Power Delay product) also reduced by 84% compared to existing ternary adders.

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Section: Carry Propagate-generate Techniquementioning

confidence: 99%

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Shanmugam¹,

Kumar²

2022

Preprint

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“…This prefix computation stage, calculates the carry signal groups directly, which uses the input and values which measured from the first stage. Carry signals generation uses the more than two inputs for which the delay is automatically increased in this process [12]. The carry propagation function and carry generation function [13] is measured by the equations (3) and (4).…”

Section: Prefix -Computationmentioning

confidence: 99%

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Daphni¹,

Grace²

2019

Adv. sci. technol. eng. syst. j.

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The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.

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“…A Manchaster carry chain-based 4-bit CLA module [13] and an 8-bit module [14] are developed for the efficient implementation of large-size CLA adders. Few PPAs are suggested [15][16][17][18][19][20][21]. In [15], Kogg and Stone have given the tree prefix algorithm to compute the intermediate carries parallelly in the tree structure and these carries are used to compute the final sum.…”

Section: Introductionmentioning

confidence: 99%

“…Further, a sparse parallel prefix carry computation method has been suggested in [18], where the group carry selection-based approach is used to reduce the hardware complexity of the PPA design. Similarly, in [19][20][21] researchers have focused to improve the design efficiency of PPA. However, the adder structures suggested for CLA and PPA [13][14][15][16][17][18][19][20][21] are efficient in terms of delay but they occupy a large area and consume more energy, whereas the structure suggested for RCA in [9,12] involves less area and energy with higher delay.…”

Section: Introductionmentioning

confidence: 99%

“…Similarly, in [19–21] researchers have focused to improve the design efficiency of PPA. However, the adder structures suggested for CLA and PPA [13–21] are efficient in terms of delay but they occupy a large area and consume more energy, whereas the structure suggested for RCA in [9, 12] involves less area and energy with higher delay. Therefore, the carry select scheme‐based adder [22] has been suggested to achieve the performance between RCA and CLA.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Area–delay and energy efficient multi‐operand binary tree adder

Patel

Singhal

2020

IET Circuits, Devices & Systems

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Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

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A review analysis of parallel prefix adders for better performnce in VLSI applications

Cited by 18 publications

References 7 publications

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Area–delay and energy efficient multi‐operand binary tree adder

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