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Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

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In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.

Parallel prefix adder (PPA) is the core component of diminished-1 modulo (2[Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo (2[Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo (2[Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.