Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder

Abstract

Parallel prefix adder (PPA) is the core component of diminished-1 modulo (2[Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo (2[Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo (2[Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array

“…In recent decades, the residue number system (RNS) [1][2][3][4][5][6] has been increasingly applied in cryptography [2,7], error correction codes [8], and digital signal processing [3], owing to its carry-free nature and parallel computation. A reduced power consumption, shorter latency, and smaller hardware area can be achieved for applications based on RNS modulation addition [9][10][11][12][13] and multiplication [14][15][16][17][18][19][20][21][22][23][24][25]. When using the multi-modulus architecture, multiple modulus operations can be performed at the same time.…”

“…Many common hardware circuits can share in the multi-modulus architecture of modulo (2 n − 1), modulo (2 n ), and modulo (2 n + 1) multipliers, owing to the commonality of the modulus and similarity of hardware circuits in the modulo multiplication, so only different modules of the circuit need to be additionally designed, which significantly reduces the circuit area. Diminished-1 representation [9,11,12] and weighted representation [13,25] are the two main representations in the RNS-based modulo multiplier. A weighted representation is adopted in the current work.…”

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

“…Therefore, the RNS has found wide application in communication systems, digital signal processors [6], digital filters [3], finite-impulse response (FIR) filters [3,7], fast Fourier transform (FFT) [7], fault-tolerant detection [11], error correction coding [11,14] and other fields [12]. Parallel-prefix adders [15] can provide a very efficient modulo arithmetic operation in RNS mathematical computation. Parallel-prefix adders [15] such as Kogge Stone adder, Sklansky adder, Ladner Fischer adder and Ling's adder are some of the most commonly used circuit architectures in modular operation.…”

“…Parallel-prefix adders [15] can provide a very efficient modulo arithmetic operation in RNS mathematical computation. Parallel-prefix adders [15] such as Kogge Stone adder, Sklansky adder, Ladner Fischer adder and Ling's adder are some of the most commonly used circuit architectures in modular operation.…”

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

“…In RNS, a large positive integer X is represented using a set of smaller integers known as residues {x1, x2,…, xN} and a set of co-prime integers known as moduli set {m1, m2,…, mN}. Addition [1][2][3] and multiplication [4][5][6] are two main basic arithmetic operations in RNS. Remarkably, RNS has non-weighted representation, such that the addition and multiplication operations can be performed simultaneously and independently in each residue channel.…”