A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

Abstract

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ∆ZTC = ZTC w/oSHE − ZTC withSHE ) is more critical at higher drain-to-source voltages (V DS ). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

“…The device consists of SiO 2 as the interfacial oxide layer and HfO 2 as the high-k gate dielectric material. Metal as the gate electrode and the spacer (Si 3 N 4 ) to suppress the gate-drain/source capacitances [17,18]. To obtain the reliable TCAD simulation results, the baseline bulk-FinFET [19] and SOI-FinFET [20] are carefully calibrated with the reported experimental data.…”

Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs

“…Synopsys Sentaurus Technology Computer Aided Design (TCAD) [18] 3D and 2D devices and mixed-mode simulations are used in this paper. The simulation setup is well calibrated by our research group [19,20] with experimental data [21,22]. The gate work functions have been tuned to 4.39 eV for the N type FinFET (nFinFET) and 4.62 eV for the Ptype FinFET (pFinFET) for the 14 nm device for the required drive current.…”

“…Other key dimensions of the FinFET device are reported in table 1. Figure 1 shows the simulated nFinFET structure for the 14 nm FinFET and its calibration with experimentally reported data [19,21]. Physical models to consider the effect of scattering phenomena due to ionized impurities, carriercarrier scattering, carrier quantization effects, high field velocity saturation effects, and the effect of lateral and perpendicular field dependence on carrier mobility are used in the simulations.…”