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A novel double gate tunnel FET with channel sandwiched by drain (CSD-TFET) is proposed and investigated in this paper. The proposed CSD-TFET consists of three differently doped drain layers in which the middle layer is an extension of the channel and is sandwiched by the heavily doped top and bottom drain layers. The objective of the proposed endeavor is to reduce the ambipolar current without affecting the ON current. We have compared the results of CSD-TFET with the reference tunnel FET (RTFET) designed by using the same simulation setup as opted for simulating the proposed CSD-TFET. The extracted ambipolar current of CSD-TFET is ∼10 4 times lower than that of RTEFT with no change in the ON current. An interesting flipping/ crossover phenomenon in the gate-to-drain capacitance (C gd ) of the proposed CSD-TFET at a certain gate-to-drain voltage (V GD ) is observed. We also discussed the saturation phenomenon of the drain current and the variation of unity gain frequency with C gd .

Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro–metal–insulator–semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal–ferro–insulator–semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance (C FE) is not a lumped capacitance. Therefore, for MFIS negative capacitance (NC) devices, the physical explanation which governs the NDR mechanism needs to be addressed. In this work, for the first time, we present the first principle explanation of the NDR effect in MFIS NC FDSOI. We found that the output current variation with the drain to source voltage (V DS), (i.e. g ds) primarily depends upon two parameters: (a) V DS dependent inversion charge gradient (∂n/∂ V DS); (b) V DS sensitive electron velocity (∂v/∂ V DS), and the combined effect of these two dependencies results in NDR. Further, to mitigate the NDR effect, we proposed the BOX engineered NC FDSOI FET, in which the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2 layer. In doing so, the inversion charge in the channel is enhanced by the BOX engineered FE layer, which in turn mitigates the NDR and a nearly zero g ds with a minimal positive slope has been obtained. Through well-calibrated TCAD simulations, by utilizing the obtained positive g ds, we also designed a V DS independent constant current mirror which is an essential part of analog circuits. Furthermore, we discussed the impact of the FE parameter (remanent polarization and coercive field) variation on the device performances. We have also compared the acquired results with existing literature on NC-based devices, which justifies that our proposed structure exhibits complete diminution of NDR, thus enabling its use in analog circuit design.

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ∆ZTC = ZTC w/oSHE − ZTC withSHE ) is more critical at higher drain-to-source voltages (V DS ). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.