An analytical model for tunnel barrier modulation in triple metal double gate tunnel FET is presented for the first time in this paper. Three different metals over the channel region assist to form a barrier in the channel which restricts the reverse tunneling of the carrier, i.e., tunneling from drain to source. The choice of three metals with different work functions helps to increase the ON-current and also to form a barrier in the channel, which reduces the OFF-current. The surface potential and the electric field are analytically modeled by solving 2-D Poisson's equation and Kane's model is used to calculate the tunneling current. The analytical results are verified with SILVACO ATLAS simulated results. Index Terms-Ambipolar behavior, band-to-band tunneling, Poisson's equation, tunnel FET (TFET), work function.Navjeet Bagga is currently pursuing the M.E. degree with the

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One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/RF and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated TCAD models, to mitigate the leakage current, we analyzed the following approach to get HVT: 1) increasing channel doping (Nch′); 2) making drain-side underlap (Ldsu); 3) increasing gate length (Lg′). Two flavors of FinFETs viz Bulk and SOI (silicon-on-insulator) are suitably compared over their baseline counterpart, i.e., without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of Bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.