2021
DOI: 10.1109/tuffc.2021.3098045
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A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation

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Cited by 23 publications
(16 citation statements)
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“…The reduction in the same is due to degradation in mobility of charge carriers at high gate bias [36]. The values obtained for I on /I off , g m , f T , TFP, g m /I ds , R out , intrinsic delay, and f max are in unison and better than [17,18,20,31,33,36]. Therefore, the proposed device shows the optimal RF/Analog performance at FE thickness of 20 nm.…”
Section: Effect Of T Fe On DC and Rf/analog Performancementioning
confidence: 77%
See 1 more Smart Citation
“…The reduction in the same is due to degradation in mobility of charge carriers at high gate bias [36]. The values obtained for I on /I off , g m , f T , TFP, g m /I ds , R out , intrinsic delay, and f max are in unison and better than [17,18,20,31,33,36]. Therefore, the proposed device shows the optimal RF/Analog performance at FE thickness of 20 nm.…”
Section: Effect Of T Fe On DC and Rf/analog Performancementioning
confidence: 77%
“…It is clear from the figure that, in saturation region with the increase in drain voltage the output current decreases showing negative differential resistance region (NDR). The same is due to increased drain electric field lines that started affecting the FE polarization at higher V ds [33]. The transconductance (g m ), which is the rate of change of I ds with applied V gs at constant drain voltage, signifies the device gain performance.…”
Section: Effect Of T Fe On DC and Rf/analog Performancementioning
confidence: 99%
“…Finally, in figure 1(b), the improvement in the device performance is presented, which is obtained for the NC-FinFET at different drain biases. The details of the calibration procedure are discussed in [11,13].…”
Section: Tcad Validation Proceduresmentioning
confidence: 99%
“…Several studies have been conducted to date to increase the performance of NC-based FETs and FinFETs, respectively. The incorporation of device engineering approaches, such as work function variability [8,9], material-structure evaluation [8,9], and spacer engineering [10][11][12][13], among others, has been published in recent years. However, the use of such variable permittivity spacers lowers the carrier mobility through the trap formation caused by Coulombic scattering [14] and affects circuit delays due to the increased fringe capacitance [15].…”
Section: Introductionmentioning
confidence: 99%
“…To counteract this impact and ensure the continuation of Moore's law in semiconductor devices, much research has been conducted on innovative device physics and structure with the goal of lowering the operating voltage of the device. [1][2][3][4][5] Although III-V materials such as GaAs, InGaAs, InP, GaAsSb, and InGaSb have gained increasing popularity among material physicists and device engineers in recent years, these materials are particularly attractive to these groups because of their wide range of applications in the area of optical and electrical devices. [6][7][8][9][10] III-V compounds such as BGaAs are extensively used for different applications such as photodetectors, solar cells, and quantum dots due to its tunable direct band gap.…”
Section: Introductionmentioning
confidence: 99%