A new rail-to-rail ultra low voltage high speed comparator

Akbari, Masoume; Maymandi-Nejad, Mohammad; Mirbozorgi, S. Abdollah

doi:10.1109/iraniancee.2013.6599850

Cited by 16 publications

(4 citation statements)

References 10 publications

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“…The comparison table also shows that the proposed comparator outperforms the other comparators in the literature up to 0.4 V supply voltage. A similar EDP at 0.3 V was reported by [48], which, however, reports no data on offset performance. Both the comparator in [48] and [46] are efficient at the 0.5 V supply.…”

Section: Comparisonsupporting

confidence: 77%

“…A similar EDP at 0.3 V was reported by [48], which, however, reports no data on offset performance. Both the comparator in [48] and [46] are efficient at the 0.5 V supply.…”

Section: Comparisonsupporting

confidence: 77%

“…The ultra-low-voltage (ULV) operation is often achieved by substituting the inverters with simple PMOS devices [28,34,[45][46][47], cross-coupled in positive feedback, or by exploiting body driving. In this case, the body terminals of the NMOS devices of the inverters can be used as input terminals, and this allows eliminating the tail current generator or the differential pair [16,22,23,45,46,48,49]. Akbari in [48] proposed a body-driven dynamic comparator where PMOS devices were used both as cross-coupled latch and as input devices, and NMOS transistors are exploited for dynamic biasing and to reset the output; the comparator is able to operate with a supply voltage as low as 0.3 V. Still lower supply voltages are reported by Yang et al [44], that present a StrongARM comparator operating in subthreshold with an auxiliary amplifier, operating down to 0.25 V, and by Li [47], where a gate-driven StrongARM exploiting cross-coupled PMOS devices as the latch is simulated down to 0.2 V supply.…”

Section: Introductionmentioning

confidence: 99%

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A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Sala

Spinogatti

Bocciarelli

et al. 2023

JLPEA

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In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.

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Section: Comparisonsupporting

confidence: 77%

“…A similar EDP at 0.3 V was reported by [48], which, however, reports no data on offset performance. Both the comparator in [48] and [46] are efficient at the 0.5 V supply.…”

Section: Comparisonsupporting

confidence: 77%

Section: Introductionmentioning

confidence: 99%

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A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Sala

Spinogatti

Bocciarelli

et al. 2023

JLPEA

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“…Table I summarizes the performance of the proposed dynamic comparator. Finally, Table II, compares the performance of the proposed comparator with the designs presented in [6], [9] and [10]. In 90nm CMOS and V DD =0.5V, the proposed comparator provides the maximum sampling of 0.33GHz while consuming 2.3µW power.…”

Section: Simulation Resultsmentioning

confidence: 99%

Analysis and design of dynamic comparators in ultra-low supply voltages

Babayan-Mashhadi

Sarvaghad-Moghaddam

2014

2014 22nd Iranian Conference on Electrical Engineering (ICEE)

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The need for ultra-low power and area-efficient analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV) dynamic clocked comparators to maximize power efficiency and speed. In this paper, a delay analysis for a conventional body-driven LV dynamic comparator is presented. Then based on the analysis results, the circuit of a conventional body-driven comparator is modified for fast operation even in small supply voltages. Simulation results in 90nm CMOS technology reveal that comparator delay time is remarkably reduced. The maximum clock frequency of the proposed comparator can be increased to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming 2.3µW and 184nW, respectively. The standard deviation of the input-referred offset voltage is 5.1mV at 0.5V supply.

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