A New 1 GS/s Sampling Rate and 400 μV Resolution with Reliable Power Consumption Dynamic Latched Type Comparator

Mahdavi, Sina; Poreh, Maryam; Ataei, Shadi; Jafarzadeh, Mahsa; Noruzpur, Faeze

doi:10.1007/978-981-10-8672-4_21

Cited by 3 publications

(1 citation statement)

References 26 publications

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“…Also in the work of Ayesh et al, a single‐ended charge steering dynamic comparator, which offers a kickback noise of 3 mV is described. In other works, other topologies of dynamic comparators are shown exhibiting different performance, although their kickback effect reduction is not quantified.…”

Section: Introductionmentioning

confidence: 96%

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Diaz‐Madrid

Doménech‐Asensi

Hauer

et al. 2019

Engineering Reports

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This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.

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Section: Introductionmentioning

confidence: 96%

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Diaz‐Madrid

Doménech‐Asensi

Hauer

et al. 2019

Engineering Reports

View full text Add to dashboard Cite

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A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Folla

Crespo

Wembe

et al. 2020

IET Circuits, Devices & Syst

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The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.

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Design Analysis of 3-Bit Flash ADC using Low-Offset and Low-Power Opamp

Saxena

Yadav

Wairya

2023

2023 10th International Conference on Signal Processing and Integrated Networks (SPIN)

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A New 1 GS/s Sampling Rate and 400 μV Resolution with Reliable Power Consumption Dynamic Latched Type Comparator

Cited by 3 publications

References 26 publications

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Design Analysis of 3-Bit Flash ADC using Low-Offset and Low-Power Opamp

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