A New Reduced Switch Seven-Level Triple Boost Switched Capacitor Based Inverter

Abstract

This paper proposes a new reduced switch count seven-level triple boost inverter based on switched capacitor technique. The proposed topology has fewer number of components and has the ability of balancing the voltage across the capacitors. The structure of the proposed topology is very simple and can be easily extended to higher number of voltage levels. The generalized structure for higher number of levels is presented. The level shifted pulse width modulation approach is used to evaluate the proposed topology. In addition, design of switched capacitors and power loss calculation of semiconductor switches are provided. This proposed inverter topology is compared with the state-of-art topologies to demonstrate its superior performance. Further, thermal modelling of the topology is done in PLECS to calculate the power losses and efficiency. Finally, this proposed 7-level topology is simulated using MATLAB/Simulink and tested on experimental prototype for the performance verification and the results are included.INDEX TERMS Switched Capacitor, multilevel inverter, DC-AC conversion, triple boost, high gain, selfvoltage balancing

A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

“…The average power loss can be estimated using the frequency and number of switching instants from the energy loss. Thus, the net loss in any inverter can be expressed in ( 16) and ( 17), 𝑃 𝐿𝑜𝑠𝑠 = 𝑃 𝑐𝑜𝑛 + 𝑃 𝑠𝑤 + 𝑃 𝑅−𝐿 (16)…”

“…While the topologies [10], [12] and [31] proposed topology, they can boost the input voltage to 1.5 times. The topology proposed in [16] can boost the input voltage to three times using ten switches, but their TSVp.u. is higher than the proposed topology.…”

“…A reduced switch count based N-Level boost inverter topology has been proposed in [14], with a boosting ability of 2, but its total standing voltage (TSV) and components to gain ration are high. The reduction is components to gain ratio is attempted in [15][16][17][18][19] for seven level output by increasing the gain to 3, but the Total standing voltage in the circuit has been compromised. Recently attempts had been made to derive different voltage levels from a single topology through symmetric or asymmetric operation.…”

A Novel Nine-Level Quadruple Boost Inverter for Electric Vehicle Applications

“…However, expanding these converters further requires highpower switches and capacitors. Topologies in [12], [13], [14], and [15] proposed target high-voltage gain, where the voltage gain of each capacitor increase in binary. However, these topologies are plagued by a high number of part count and blocking voltage issues.…”

“…However, further expansion of these converters demands high-power switches and capacitors. On the other hand, topologies proposed by Wang et al [12], Kovvali et al [13], Siddique et al [14], and Taghvaie et al [15] aimed at high-voltage boosting, wherein the voltage gain of each capacitor increases in a binary manner. Nonetheless, these topologies suffer from a high number of semiconductors and blocking voltage.…”