A new salicide process (PASET) for sub-half micron CMOS

Abstract

A new Ti salicide process featured by ~e-&norphizdtion before Ti film deposition and SEquential Two step sintering(PASET) has been proposed for sub-half micron CMOS. Pre-amorphization by As implantation can realize low and uniform sheet resistance TiSi2 on highly As doped n+ poly and diffusion layers with sub-half micron line width. Implanted As for pre-amorphization and sequential two step sintering prevents the TiSi2 overgrowth on p+ poly and diffusion layers. The PASET widens the process window in process integration. The resulting n-and p-MOSFETs show excellent characteristics. IntroductionSelf-aligned silicide(sa1icide) is one of the most important technologies for the realization of sub-half micron VLSI circuits with low series resistance in the poly and diffusion layers.However, the conventional Ti salicide process has the following difficulties. First, when the As concentration is increased to avoid the depletion layer formation in the poly gate, the sheet resistance of TiSi2 on As doped poly increases. Although the sheet resistance may be reduced by the high temperature sintering, the process window for this treatment is quite narrow. Because the overgrowth of TiSi2 on p+ regions is serious. Second, as is well known, the sheet resistance of TiSi2 on highly As doped poly increases, as line width decreases(1). This is the serious problem for VLSI devices with sub-half micron rule and beyond.Several proposals have been reported up to now to overcome the above mentioned difficulties. For example, Si ion beam mixing technique is effective to reduce the sheet resistance of TiSi2(2). However, Ti knock-on during Si ion implantation increases leakage current for shallow junctions. As another example, sequential deposition of Ti and amorphous Si is proposed to enhance the silicide reaction by avoiding the formation of the native oxide at Ti and Si interface(3). However, the process requires specifically designed equipment and would not be practical.This paper proposes a new salicide process;PASET. This technology produces TiSi2 with low sheet resistance even on fine line poly and diffusion layers, through wide process windows. CMOS devices with 0.3Spm rule are successfully developed by employing the PASET process technology.

Titanium-based ohmic contacts in advanced CMOS technology

“…This is also called the famous 'fine line effect' [52][53][54]. Although tremendous efforts such as high-temperature deposition [56][57][58][59], PAI [53,[60][61][62][63] and metal impurity/interlayers [64][65][66][67] have been made to enhance the transformation from C49-TiSi 2 to C54-TiSi 2 , C54-TiSi 2 with low resistivity is still replaced by CoSi 2 and Ni(Pt)Si in 0.18 µm and beyond nodes.…”

On the Manifestation of Ge Pre-Amorphization Implantation (PAI) in Forming Ultrathin TiSixfor Ti Direct Contact on Si in Sub-16/14 nm Complementary Metal-Oxide-Semiconductor (CMOS) Technology Nodes

“…For aggressively downscaled Complementary Metal-Oxide-Semiconductor (CMOS) devices, the contact resistance between silicide and Si/SiGe is becoming a significant contribution to both the intrinsic device resistance and the parasitic external resistance, thus affecting the driving capability and RC delay. 1 In state-of-the-art 3D FinFET devices from the 22 nm node, Ti-based silicide, employed previously as the source/drain (S/D) contact material in 0.35-0.18 μm technology nodes, [2][3][4][5][6][7][8][9][10] has resurged in the manufacturing and research community. [11][12][13][14][15][16][17][18][19] For FinFET devices, the 3D architecture imposes unique constraints for the selection of S/D contact materials.…”

Solid phase reaction of Ti with Si−Ge layers prepared by Ge-implantation

“…10 In normal Ti-silicides, it is established that the silicidation process suffers from increasing difficulty in the formation of low resistance silicides in very thin and narrow sub-micron lines due to the increase of C49 to C54 phase polymorphic temperature beyond the agglomeration temperature. [14][15][16] Recently, preamorphization implantation with Ge is shown to offer a low thermal budget silicide process with efficient control of silicide thickness through preamorphized layer. [14][15][16] Recently, preamorphization implantation with Ge is shown to offer a low thermal budget silicide process with efficient control of silicide thickness through preamorphized layer.…”