A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder

Marienfeld, D.; Sogomonyan, E.S.; Ocheretnij, V.; Gössel, Michael

doi:10.1109/etsym.2004.1347594

Cited by 10 publications

(17 citation statements)

References 15 publications

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“…For other regular structures, such as different types of multipliers or dividers, similar results can be obtained -as recently published in the literature [8,9,10].…”

Section: • Fault Tolerancesupporting

confidence: 77%

“…Both the circuit outputs y 1 and y 2 are simultaneously erroneous if the error is stimulated by x 1 = 0 and simultaneously propagated along the paths G 1 , G 2 , G 3 , G 4 and G 1 , G 5 , G 6 , G 7 and G 8 . This is only possible if the side inputs of both of these paths are the non-controlling values x 2 = 1, x 3 = 0, x 4 = 1 and x 2 = 1, x 6 = 1,…”

Section: Fig 22 An Example Of a Combinational Circuitmentioning

confidence: 99%

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New Methods of Concurrent Checking

Sogomonyan¹

2008

Frontiers in Electronic Testing

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“…For other regular structures, such as different types of multipliers or dividers, similar results can be obtained -as recently published in the literature [8,9,10].…”

Section: • Fault Tolerancesupporting

confidence: 77%

Section: Fig 22 An Example Of a Combinational Circuitmentioning

confidence: 99%

New Methods of Concurrent Checking

Sogomonyan¹

2008

Frontiers in Electronic Testing

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“…The parity of the propagated signals P is checked by the input parity. As shown in (Marienfeld et al, 2004), a parity-checked carry-saveadder can be combined efficiently with a final sum-bit duplicated carry-dependent CPA to increase the error detection capability of a multiplier. …”

Section: Self-checking Addersmentioning

confidence: 99%

“…In both multipliers, as a final Carry-Propagate-Adder (CPA), a sum-bit duplicated Carry-Ripple-Adder (CRA) conforming to (Marienfeld et al, 2004) is used together with parity prediction of a Carry-Save-Adder (CSA) consisting of carry-depended adder cells and realizing the standard sign extension.…”

Section: Introductionmentioning

confidence: 99%

New Self-Checking Booth Multipliers

Hunger¹,

Marienfeld²

2008

International Journal of Applied Mathematics and Computer Science

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This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

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“…Therefore, these faults must be detected during the operation of the circuit. Generally, transient faults can be detected by self-checking circuits, [5][6][7][8][9] built-in fault detection, and correction circuits [10][11][12][13][14][15][16][17][18][19][20][21] . By using the built-in fault detection and correction circuits, the transient faults can be tolerated during the run time.…”

Section: Introductionmentioning

confidence: 99%

A Multi-Stage Fault-Tolerant Multiplier With Triple Module Redundancy (Tmr) Technique

Chen

Shyu

et al. 2014

J CIRCUIT SYST COMP

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In this study, a multistage fault-tolerant (MSFT) scheme for two¯xed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost faulttolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-m CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 Â 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 Â 64 Type-I MSFT multiplier is only 0:21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 Â 64 Type-II MSFT multiplier

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A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder

Cited by 10 publications

References 15 publications

New Methods of Concurrent Checking

New Methods of Concurrent Checking

New Self-Checking Booth Multipliers

A Multi-Stage Fault-Tolerant Multiplier With Triple Module Redundancy (Tmr) Technique

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