A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology

Noruzpur, Faeze; Mahdavi, Sina; Poreh, Maryam; Ghasemi, Shima Tayyeb

doi:10.23919/mixdes.2018.8443590

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…Although faster links beyond 60 Gbps are beginning to replace the 10-25-Gbps ports, 10-25 Gbps is still the mainstream data rate in the industry. Because of the increase in the data rate of the SerDes system, the PLL design has encountered more challenges, such as a high-frequency design and a wide frequency-tuning range with a low-jitter design [3][4][5][6][7]. Ring PLL and LC PLL are the two most widely used integrated on-chip PLLs.…”

Section: Introductionmentioning

confidence: 99%

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

et al. 2021

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This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

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