A New Symmetric Cascaded Multilevel Inverter Topology Using Single and Double Source Unit

Ali, Jagabar Sathik Mohamed; Kannan, Ramani

doi:10.6113/jpe.2015.15.4.951

Cited by 20 publications

(7 citation statements)

References 32 publications

(41 reference statements)

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“…In this aspect, required number switches, gate drivers, dc sources, and total standing voltage are considered as key parameters for the performance assessment. However, multilevel inverters synthesize different voltage levels in a symmetric and asymmetric configuration; for a reasonable comparison, the 13-level proposed topology is examined with conventional and recent topologies [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24] in a similar output-level operation.…”

Section: Comparison Of the Proposed Topology With The Existing 13-lev...mentioning

confidence: 99%

“…Even though it uses a lower number of switches, gate driver circuits, and dc sources, the sub multilevel inverter can generate a unidirectional multistep output waveform. In order to obtain the polarity change of the sub multilevel inverter output, a back end H-bridge circuit is connected, and its switches are capable of withstanding the sum of dc source value available in each unit [14]. Another attempt is made with the development of switched-capacitor topology, in which the combination of dc sources and capacitors is used in different voltage ratios to reduce the required dc sources.…”

Section: Introductionmentioning

confidence: 99%

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Compact Thirteen-Level Inverter for PV Applications

Prathaban

Karthikeyan

Abubakar³

2022

Energies

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In renewable energy source applications, multilevel inverters with lower power components have become more popular in recent decades. This work exhibits a novel topology for high-quality output in PV applications, along with low-power switches and isolated dc sources. The core module of the suggested design may create a 13-level output waveform with two unequal voltage source values. The cascaded structure is intended to boost the voltage levels, and the related parameters are obtained analytically. The even and odd levels of voltage can be created natively without the usage of an additional H bridge circuit. Furthermore, the switches, gate driver circuits, dc sources, and standing voltage are fewer in number when compared to other recent topologies. Power losses and cost comparisons are calculated and given in monetary terms. This new research supports the idea that nearest level control (NLC) is used as a modulation scheme in the simulation modeling and experimental validation of the proposed topology.

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Section: Comparison Of the Proposed Topology With The Existing 13-lev...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compact Thirteen-Level Inverter for PV Applications

Prathaban

Karthikeyan

Abubakar³

2022

Energies

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“…It is evident from Figure 6c, m = 1 presents the optimal topology for generating more levels with constant Dc sources for both algorithms. The Equations ( 20)- (22) and Equations ( 23)- (25) provides the relation between the number of switches, number of drivers, and number of DC sources to the number of levels for the first and second algorithm respectively.…”

Section: Optimization Of the Proposed Cascade Converter For Maximizin...mentioning

confidence: 99%

“…The higher number of switches makes this circuit impractical. All the topologies discussed above have a common issue of higher device count [22][23][24][25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

A New Multilevel Inverter Topology with Reduced DC Sources

Rawa

Prem²,

Ali

et al. 2021

Energies

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The component count for the multilevel inverter has been a research topic for the last few decades. The higher number of power semiconductor devices and sources leads to a higher power loss with the complex control requirement. A new multilevel inverter topology employing the concept of half-Bridge modules is suggested in this paper. It requires a lower number of dc sources and power components. The inverter is controlled using a fundamental frequency switching scheme. With the basic unit being able to produce 13 level voltage waveforms with three dc voltage sources, higher-level inverter configuration has also been discussed in the paper. The performance of the topology is analyzed in the aspects of circuit parameters and found better when compared to similar topologies proposed in recent literature. The comparison provided in the paper set the benchmark of the proposed topology in terms of lower component requirements. The topology is also optimized with two voltage fixing algorithms for maximizing the number of levels for the given number of IGBTs, drivers and dc sources, and the observations are presented. The efficiency analysis gives the peak efficiency as 98.5%. The simulations were carried out using the PLECS software tool and validated using a prototype rated at 500 W. The results with several test conditions have been reported and discussed in the paper.

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“…Reducing the switch count for the design of multilevel inverters (MLIs) has an area of research in MLIs and focused to the study on reduced switch multilevel inverters (RSMLIs) (Vemuganti et al, 2018) (Ali and Kannan, 2015;Prabaharan and Palanisamy, 2017). RSMLIs are also designed by symmetric and asymmetric voltage sources with and without H bridge circuits.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Switching Sequence Operation for Reduced Switch Multilevel Inverter With Various Pulse Width Modulation Methods

Kanike

Raju

2020

Front. Energy Res.

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Pulse width modulation (PWM) methods are used to control the switching sequence operations of conventional multilevel inverters (MLIs) and reduced switch multilevel inverters (RSMLIs). Many researchers proposed various RSMLIs with their switching sequence operation and PWM control techniques. However, the switching operations of RSMLIs are not similar to conventional MLIs, which are a major problem of switch control. Logical equations are proposed for the operation of RSMLIs with the multi-carrier PWM methods like alternative phase opposition disposition (APOD), phase opposition disposition (POD), and phase disposition (PD). To operate the individual switch in symmetrical and asymmetrical RSMLI, logical operators are used to produce required pulse sequence from the sequence of PWM method and their analysis is not present in previous works. The proposed methodology can be applied to PV systems for efficient operation. The proposed methodology and binary representation of PWM method are analyzed on various RSMLIs for seven-level output voltage to operate each individual switch. Control of individual switching sequence and the operation of RSMLIs are simulated using MATLAB/Simulink. THD comparison is presented for RSMLI, DCL MLI, and SCSD MLI with various PWM methods.

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A New Symmetric Cascaded Multilevel Inverter Topology Using Single and Double Source Unit

Cited by 20 publications

References 32 publications

Compact Thirteen-Level Inverter for PV Applications

Compact Thirteen-Level Inverter for PV Applications

A New Multilevel Inverter Topology with Reduced DC Sources

Analysis of Switching Sequence Operation for Reduced Switch Multilevel Inverter With Various Pulse Width Modulation Methods

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