A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

Hanchate, N.; Ranganathan, N.

doi:10.1109/icvd.2004.1260929

Cited by 15 publications

(11 citation statements)

References 11 publications

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“…The core of the sizing algorithm is Lines (6)(7)(8)(9)(10)(11)(12). We selectively replace the selected gate by all alternatives, one at a time.…”

Section: B Leakage Optimization Flowmentioning

confidence: 99%

“…Body-biasing [19], which can be applied on a circuit block, can be used to alter the operating frequency and leakage current proportionally, depending on whether the block is in active or idle mode. Transistor stacking [9], which is based on the fact that two transistors stacked in series in off-mode exhibit less leakage current than one transistor with the double channel length, has been shown to be able to reduce leakage. Gate sizing and buffer insertion [15] has also accepted a lot of attention both for deterministic and statistical delay and power optimization.…”

Section: Introductionmentioning

confidence: 99%

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Statistical Timing-Based Post-Placement Leakage Recovery

Kounalakis

Sotiriou

Zebilis

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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This work presents a post-placement, leakagerecovery methodology, based on gate resizing, which supports and preserves statistical constraints, i.e. a (mean, sigma) constraint pair during leakage optimization. We exploit statistical models for delay and leakage, which utilize normal and lognormal distributions respectively. The distributions are extracted by extrapolating process, temperature and voltage data. Our leakagerecovery is based on statistical wire delay bounds generated for a (sigma, mean) constraint by the TSZSA algorithm and redistributed across gates using an ILP-based slack reassignment strategy. Available gate slack is converted into reduced leakage by downsizing the relevant gates, while preserving the statistical slack assignment. Experimental results, on the IWLS 2005 benchmarks, indicate an average of over %20 leakage recovery with no timing yield loss, where similar leakage gains for a non-statistical, state of the art leakage recovery tool present an average of over %6 loss in timing yield. We also illustrate that our gate resizing algorithm exploits a delay-leakage trade off, for a fixed sigma value.

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“…The core of the sizing algorithm is Lines (6)(7)(8)(9)(10)(11)(12). We selectively replace the selected gate by all alternatives, one at a time.…”

Section: B Leakage Optimization Flowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Statistical Timing-Based Post-Placement Leakage Recovery

Kounalakis

Sotiriou

Zebilis

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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“…With the development of the technology towards submicron region leakage power has become significant component of total power dissipation [7].In this paper, comparison of CMOS technology & transmission gate logic based on 90 nm technology with the help of XOR gate. The main advantage of the TG logic is complex logic functions are implemented by using small number of transistors.…”

Section: Introductionmentioning

confidence: 99%

Design of Area and Power Efficient Half Adder Using Transmission Gate

Anand¹

2015

IJRET

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This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors.

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“…The leakage power of CMOS circuits is determined by the leakage current [12], [13] when the input voltage is less than threshold voltage and transistor is off state (standby mode) but there is leakage of current from Drain to ground. With the development of technology leakage power has become significant component of total power dissipation [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power High Speed Level Shifter

Srinivasulu¹

2014

IJRET

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The leakage power consumption increases with the scaling of the devices and it is expected that the leakage power consumption is important design constraint of total power consumption. In this proposed work , a new configuration of level shifter for low power high speed application has been presented. The proposed circuit ha ve n o cross co u p led con n ection , by which there will be reduction in delay. In this work a new level shifter design has introduced at an ultra low core voltage and has wide range of Input/output voltage. This Low power high speed level shifter allows wide Input/output interface voltage applications in CMOS Technology. On an average it shows an improvement of 8% on average power consumption and 77.2% on delay compared with conventional level shifter with a little bit area overhead.

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A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

Cited by 15 publications

References 11 publications

Statistical Timing-Based Post-Placement Leakage Recovery

Statistical Timing-Based Post-Placement Leakage Recovery

Design of Area and Power Efficient Half Adder Using Transmission Gate

Design of Low Power High Speed Level Shifter

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